Fault-tolerant architecture and method for complex convolutional neural network

Abstract

The invention relates to the technical field of network data communication fault tolerance, and discloses a complex convolutional neural network-oriented fault tolerance architecture and method.The complex convolutional neural network-oriented fault tolerance architecture comprises an AET brain-like fault tolerance architecture and a convolutional neural network, the AET brain-like fault tolerance architecture comprises an AET cluster, the AET cluster comprises a plurality of nodes which are connected together, and the convolutional neural network is connected with the AET cluster. A volume base layer, a pooling layer and a full connection layer of the convolutional neural network are mapped to different nodes in a chain structure to form chain mapping nodes, nodes without a mapping relation are used as idle nodes, and when the nodes with the mapping relation have errors, the idle nodes close to the nodes with the mapping relation take over the errors to perform operation and communication tasks; according to the architecture, when an error node occurs, a nearby idle node substitutes for the error node, so that data delay caused by excessive data transmission when the idle node is searched for is avoided, substitution from the idle node to the mapping node can be quickly completed, a new connection architecture is formed, time sequence stability of a network is ensured, and data communication is completed more efficiently.

Description

technical field [0001] The invention relates to the field of network data communication fault-tolerant technology, in particular to a fault-tolerant architecture and method for complex convolutional neural networks. Background technique [0002] The AET (Autonomous Error Tolerant, autonomous fault-tolerant) structure simulates the connection between neurons in the human brain through mutual communication to form a brain-like structure, thereby obtaining a more effective fault-tolerant solution in terms of performance and considering power consumption. And the lower cost of the chip area, but when the AET structure is fault-tolerant, the scale of the system is limited, because when the scale of the AET processing unit cluster continues to increase, this structure will appear the key AET processing unit, once the processing A unit error will cause long-term communication in the global wiring, which will lead to problems such as communication blocking, delay, and communication ...

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Problems solved by technology

[0002] The AET (Autonomous Error Tolerant, autonomous fault-tolerant) structure simulates the connection between neurons in the human brain through mutual communication to form a brain-like structure, thereby obtaining a more effective fault-tolerant solution in terms of performance and considering power consumption. And the lower cost of the chip area, but when the AET structure is fault-tolerant, the scale of the system is limited, because when the scale of the AET processing unit cluster continues to increase, this structure will appear the key AET processing unit, once the processing Unit errors will cause long-term communication in the global wiring, which will lead to problems such as communication blocking, delay, and communication efficiency reduction.

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