Instruction prefetching method and device, equipment and medium

Abstract

The invention discloses an instruction prefetching method and device, equipment and a medium, and relates to the data storage technology, and the method comprises the steps that before a processor core obtains a needed instruction from a target buffer area corresponding to the processor core, the instruction in the target buffer area is pre-compiled; if it is determined that the jump instruction exists in the target buffer area according to the pre-compilation result, and the branch instruction with the jump instruction is not cached in the target buffer area, the branch instruction which is not cached is prefetched from the instruction cache region to a candidate buffer region corresponding to the processor core so as to wait for the processor core to obtain the branch instruction from the candidate buffer region, wherein the target buffer area and the candidate buffer area are alternately multiplexed in the instruction prefetching process. According to the embodiment of the invention, on the basis of not increasing the processing and manufacturing cost of the processor, the instruction fetching efficiency of each processor core can be improved, the instruction fetching time delay can be reduced, and the influence of the coverage of the cache instruction on the operation of the processor can be reduced.

Description

technical field [0001] The embodiments of the present application relate to computer technology, in particular to data storage technology, and in particular to an instruction prefetching method, device, device, and medium. Background technique [0002] Prefetching instruction operations are widely used in various processors to achieve the purpose of improving processor performance. At present, for multi-core processors, prefetch instruction operations are mainly implemented in the following two ways: [0003] Solution 1: Adding a first-level register cache in each processor core, the cache size is generally the read path bandwidth of the instruction cache area (icache). Read multiple instructions from icache at a time and store them in the increased register cache, and continue to read multiple instructions from icache after the instructions in the register cache are used up. When operations such as instruction branching and jumping occur in each processor core, if the jum...

AI Technical Summary

Problems solved by technology

However, adding one level of icache to each processor core will undoubtedly increase the overall area of ​​the processor and increase the processing and manufacturing cost of the processor

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