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Multi-emission method of instructions in high-performance DSP (digital signal processor)

A processor and high-performance technology, applied in the direction of concurrent instruction execution, machine execution device, etc., can solve the problems of processor performance not being able to compete with chips, and key technologies being controlled by others, so as to improve performance, improve instruction fetch efficiency, and improve launch efficiency. Effect

Active Publication Date: 2014-08-27
58TH RES INST OF CETC
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Problems solved by technology

However, since our country started late in this field, the developed processors are still unable to compete with foreign chips in terms of performance and specific practical applications, and are still subject to others in some core key technologies.

Method used

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  • Multi-emission method of instructions in high-performance DSP (digital signal processor)
  • Multi-emission method of instructions in high-performance DSP (digital signal processor)
  • Multi-emission method of instructions in high-performance DSP (digital signal processor)

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with drawings and embodiments.

[0020] Instruction multiple emission method in the high-performance DSP processor of the present invention, step is as follows:

[0021] a. The CPU fetching unit issues the fetching address and fetches the required instruction from the instruction cache; if the instruction cache is missing, it fetches the instruction from the external storage unit and updates the corresponding cache line; each time the CPU fetching unit fetches 64-bit sized instructions;

[0022] b. Align the fetched instructions and put them into the prefetch buffer. The total size of the prefetch buffer is 128 bits, which consists of eight 16-bit prefetch buffers: prefetch buffer 0, prefetch buffer 1, ...prefetch buffer 7. The prefetch buffer aligns the instructions according to the offset bits of the CPU instruction fetch address, aligns the instruction fetched by the value fetch unit for the first...

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Abstract

The invention discloses a multi-emission method of instructions in a high-performance DSP (digital signal processor). A multi-emission mechanism is realized by comprising an organization structure of an instruction Cache, instruction aligning and pre-fetching and a multi-emission device of the instructions, wherein the organization structure of the instruction can support fetching of a plurality of instructions, in the aligning and pre-fetching of the instructions, and the required instruction can be located rapidly according to a fetching address transmitted by the CPU (central processing unit); and the multi-emission device of the instructions can transmit the instructions to a corresponding assembly line according to the types of the instructions. The multi-emission method disclosed by the invention has the advantages that the efficiency of fetching and emitting the instructions can be improved, thereby improving the overall performance of the DSP.

Description

technical field [0001] The invention relates to the design of a DSP processor core, in particular to a multi-instruction instruction method in a high-performance DSP processor. Background technique [0002] Digital Signal Processor DSP (Digital Signal Processor) is a microprocessor specially used for digital signal processing, which can quickly complete the algorithm processing of various digital signals in real time. Because DSP has the characteristics of fast response and high-speed calculation, it has been widely used in consumer electronics, communications, aerospace and national defense security and other fields. The rapid development of DSP microprocessors has had a huge impact on national defense security and people's daily life. [0003] The research and development of high-performance DSP processors is a high point in the competition of scientific and technological strength of various countries in the world. Our country now also attaches great importance to the fie...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
Inventor 杨晓刚张庆文黄嵩人屈凌翔
Owner 58TH RES INST OF CETC
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