A network processor instruction storage device and the instruction storage method of the device

Abstract

An instruction storage device of a network processor and an instruction storage method for same. The device comprises: quick memories (Qmems), buffers, a first low-speed instruction memory and a second low-speed instruction memory. The network processor comprises more than two micro engine large groups, each micro engine large group comprising N micro engines, and the N micro engines being divided into more than two micro engine subgroups; each micro engine corresponds to one Qmem and one buffer, the Qmem being connected to the micro engine, and the buffer being connected to the Qmem; each micro engine subgroup corresponds to one first low-speed instruction memory, the buffer corresponding to each micro engine in the micro engine subgroup being connected to the first low-speed instruction memory; and each micro engine large group corresponds to one second low-speed instruction memory. In this solution, a high instruction fetch efficiency is ensured, a large amount of hardware storage resources is saved, and the realization of a compiler is made simpler.

Description

technical field [0001] The invention relates to the Internet field, in particular to a network processor instruction storage device and an instruction storage method of the device. Background technique [0002] With the rapid development of the Internet (Internet), the interface rate of the core router used for backbone network interconnection has reached 100Gbps. This rate requires the line card of the core router to be able to quickly process the messages passing through the line card. Currently, most industries use multi-core networks. The structure of the processor. The fetching efficiency of instructions is a key factor affecting the performance of multi-core network processors. [0003] In a network processor system with a multi-core structure, the same group of micro engines (Micro Engine, ME for short) has the same instruction requirements. Due to the limitation of chip area and process, it is impossible to equip each micro engine with an exclusive storage space to ...

AI Technical Summary

Problems solved by technology

When jump instructions account for a large proportion, a large number of empty instructions need to be inserted, resulting in a lot of waste of instruction space, and also increasing the complexity of compiler implementation

This solution requires that all RAMs can return data within one clock cycle, which must be implemented with SRAM, but the use of a large number of SRAMs also causes a large amount of resource overhead

Images