Signal processing circuit and memory with channel ecc

Abstract

The embodiment of the present application provides a signal processing circuit and memory with channel ECC, wherein the data transmission line includes: an external data line for transmitting data and an ECC check code; an error detection module for checking the external data line Perform error detection and / or error correction on the transmitted data, and output corrected data; a judgment module, used to output the first control signal; a statistics module, used to output the second control signal; a data buffer module, used to output the first control signal according to the first The control signal transmits the corrected data output by the error detection module to the global data line or flips the corrected data output by the error detection module and then transmits it to the global data line; the write module controls the data transmission in the global data line to the local data line, and based on the third control signal, it is judged whether the data in the global data line is transferred to the local data line in the process of data inversion; the application aims to reduce the low power consumption of the signal processing circuit and improve the reliability of data storage sex etc.

Description

Signal processing circuit and memory with channel ECC technical field The application relates to the field of semiconductor circuit design, particularly a kind of signal processing circuit and memory containing channel ECC storage. Background technique Dynamic random access memory (Dynamic Random Access Memory, DRAM) due to its high storage density, transmission It has the characteristics of fast transmission speed and so on, and is widely used in modern electronic systems. With the development of semiconductor technology, DRAM technology is more and more advanced In addition, the integration of memory cells is getting higher and higher; at the same time, various applications have also affected the performance, power consumption and reliability of DRAM. are increasingly demanding. And the existing memory with channel error detection and correction function (linkError Correcting Code, linkECC) Data transmission lines still have room for improvement in terms of po...

AI Technical Summary

Problems solved by technology

[0003] However, there is still room for improvement in terms of power consumption and reliability of existing memory data transmission lines with channel error detection and correction functions (linkError Correcting Code, linkECC). It is urgent to design a method that can reduce data transmission power consumption and improve storage reliability. The comprehensive performance of the existing ECC memory is further improved to meet the needs of various application scenarios

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