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A chip packaging structure and chip packaging method

A chip packaging structure, chip technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of poor reliability of chip packaging structure, etc., to reduce the impact of chip offset, reduce usage, reduce warping The effect of curvature

Active Publication Date: 2022-07-19
NAT CENT FOR ADVANCED PACKAGING CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Therefore, the technical problem to be solved by the present invention is to overcome the problem of poor reliability of the chip packaging structure of chips in the prior art, thereby providing a chip packaging structure and a chip packaging method

Method used

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  • A chip packaging structure and chip packaging method
  • A chip packaging structure and chip packaging method
  • A chip packaging structure and chip packaging method

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Embodiment Construction

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must hav...

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Abstract

The invention provides a chip packaging structure and a chip packaging method. The chip packaging structure includes: a first redistribution structure; The accommodating cavity; the chip located in the accommodating cavity, the front side of the chip is electrically connected to the first redistribution structure; the plastic sealing layer, the plastic sealing layer is filled in the accommodating cavity and surrounds the chip. The chip is arranged in the accommodating cavity running through the first wafer, the chip occupies the space of the first wafer, and the plastic sealing layer is filled in the accommodating cavity and surrounds the chip, which greatly reduces the usage of the plastic sealing layer, The influence of chip offset caused by thermal expansion and contraction of the material of the plastic encapsulation layer can be reduced, and the warpage of the wafer can be reduced at the same time. In addition, the accommodating cavity penetrates the first wafer, providing a deformation space for the plastic sealing layer, and the stress of the plastic sealing layer can be better released to avoid backlog of chips. In conclusion, the reliability of the chip package structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a chip packaging method. Background technique [0002] CoWoS (Chip-on-Wafer-on-Substrate) packaging is a technology that encapsulates chips and substrates together, and is performed at the wafer level. After the chip is bonded to the wafer, the plastic encapsulation layer of the plastic encapsulated chip is formed. Since the plastic encapsulation layer uses a large amount of epoxy plastic encapsulant, the epoxy plastic encapsulant is easily deformed by thermal expansion and contraction, which directly leads to the chip covered by the plastic encapsulation layer. Offset and wafer warpage problems occur. SUMMARY OF THE INVENTION [0003] Therefore, the technical problem to be solved by the present invention is to overcome the problem of poor reliability of the chip packaging structure of the prior art chip, thereby providing a chip packaging...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L23/31H01L21/56
CPCH01L23/485H01L23/3107H01L21/56H01L2224/16225
Inventor 曾淑文曹立强张春艳
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD