Source driver and display device
A source driver and source line technology, applied to instruments, static indicators, etc., can solve the problem of image quality degradation and achieve the effect of suppressing uneven brightness
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0030] figure 1 It is a block diagram showing the configuration of the display device 100 of the present invention. The display device 100 is a liquid crystal display device of an active matrix driving method. The display device 100 includes a display panel 11, a display controller 12, gate drivers 13A and 13B, and source drivers 14-1 to 14-p.
[0031] The display panel 11 is composed of a plurality of pixel portions P arranged in a matrix. 11 ~P nm and pixel switch M 11 ~ M nm (n, m: natural numbers greater than or equal to 2) semiconductor substrate configuration. The display panel 11 has n gate lines GL1 to GLn and m source lines SL1 to SLm arranged to intersect them. In the following description, any one of the n gate lines GL1 to GLn may be described as the gate line GLk, and any one of the m source lines SL1 to SLm may be described as The source line is described as the case of the source line SLx. Pixel part P 11 ~P nm and pixel switch M 11 ~ M nm They are p...
Embodiment 2
[0094] Next, Example 2 of the present invention will be described. The display device of the second embodiment differs from the display device 100 of the first embodiment in the internal structure and operation of the timing control section 24 of the source driver IC. In the following description, the IC constituting the source driver 14-1 is referred to as IC1, and the IC constituting the source driver 14-y located in the center among the source drivers 14-1 to 14-p is referred to as IC1. for ICy.
[0095] Figure 7 It is a block diagram showing the internal configuration of the timing control unit 24 of the display device according to the second embodiment together with the source control core 20 and the data latch unit 21 . The timing control unit 24 has a gate line counter 31 , a register 32 , a gate line direction output delay timing generation unit 41 , a source line direction output delay timing generation unit 42 , and a setting signal addition unit 43 .
[0096] Th...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


