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Labeling method and device for low-reliability failure die of wafer

A reliability and die technology, applied in the field of chip manufacturing, can solve the problems of omission, wrong killing, yield failure and so on

Active Publication Date: 2021-07-16
深圳智现未来工业软件有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some yield failures cannot find the root cause in time, sometimes the same failure will lead to different yield failure modes, and different reliability engineers make different judgments, which may cause overkill or miss introduce risk

Method used

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  • Labeling method and device for low-reliability failure die of wafer
  • Labeling method and device for low-reliability failure die of wafer
  • Labeling method and device for low-reliability failure die of wafer

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Embodiment Construction

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] The low reliability problem refers to the problem of unstable chip performance. Although some chips may pass the functional test without showing functional problems in the early functional test, they are prone to failure or even unusable in the later use, so they need to be identified and discarded during the chip generation process. A...

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Abstract

An embodiment of the invention provides a labeling method for a low-reliability failure die. The method comprises the steps of: acquiring a wafer graph through a wafer function test; according to the wafer graph, determining whether a regional die failure exists on a wafer corresponding to the wafer graph; when regional die failure exists, determining a first target die, wherein the first target die is located in an region adjacent to a failure region corresponding to the regional die failure, and the first target die passes the function test; and judging whether at least a first preset number m of failure dies exist in adjacent dies surrounding the first target die, and if so, performing low-reliability failure labeling on the first target die.

Description

technical field [0001] The invention relates to the field of chip manufacturing, in particular to a method and device for labeling low-reliability failed dies of a wafer. Background technique [0002] In the manufacturing process of micro-electromechanical system chips, because the online yield test cannot 100% cover all the situations in which the chip is actually used, when a yield failure occurs on the wafer, some chips that pass the functional test will still have reduced reliability. Case. Whether these chips with doubtful reliability should be discarded as failed chips or processed as normal chips is usually determined by a reliability engineer (Quality and Reliability Engineer) based on the cause of yield failure, past experience, and engineering judgment. Some yield failures cannot find the root cause in time, sometimes the same failure will lead to different yield failure modes, and the judgments made by different reliability engineers are also different, which may...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L21/67G01R31/26
CPCH01L22/20H01L22/14H01L21/67282G01R31/2642
Inventor 易丛文徐文丞林孟喆戴静安
Owner 深圳智现未来工业软件有限公司