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Super-junction MOS type device with terminal protection region

A technology of terminal protection area and terminal area, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of uneven distribution of impurities on the side of super-junction P-pillars, low withstand voltage of super-junction power device terminals, etc., and optimize the device surface Electric field, reducing junction curvature effect, effect of impurity distribution leveling

Pending Publication Date: 2021-08-20
SICHUAN BLUE COLOR ELECTRONICS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a super-junction MOS device with a terminal protection area, in order to solve the problems of uneven distribution of impurities on the side of the super-junction P-pillar and low terminal withstand voltage of super-junction power devices

Method used

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  • Super-junction MOS type device with terminal protection region
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  • Super-junction MOS type device with terminal protection region

Examples

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Effect test

Embodiment 1

[0040] Embodiment 1 A super junction MOS device with a terminal protection region

[0041] Such as Figure 1 ~ Figure 3As shown, this embodiment includes a cell area 1 that is a rounded rectangle in the top view and a terminal area 2 that is a rounded rectangular ring in the top view around the cell area 1. The terminal area 2 and the cell area 1 share N + Substrate 3 and N-type epitaxial layer 4.

[0042] Wherein, the terminal area 2 is divided into a terminal transition area and a terminal non-transition area which are distributed sequentially along the radiation direction from the edge of the cell area 1 to the edge of the device, both of which are rectangular rings with rounded corners in the top view. The terminal transition region includes three mutually independent first silicon oxide regions 5 located in the N-type epitaxial layer 4, a first P-type silicon oxide region surrounding each first silicon oxide region 5 and having a depth smaller than that of the first sili...

Embodiment 2

[0055] Embodiment 2 A super junction MOS device with a terminal protection region

[0056] The structure of this embodiment is basically the same as that of Embodiment 1, the difference is that, as Figure 5 As shown, in this embodiment, the top views of the third silicon oxide region 13 and the third silicon oxide region 13 are both square, and the top views of the third P-type doped column 14 and the fourth P-type doped column 20 are both square rings. .

Embodiment 3

[0057] Embodiment 3 A super junction MOS device with a terminal protection region

[0058] The structure of this embodiment is roughly the same as that of Embodiment 1, and it is an improvement on the basis of Embodiment 1. The difference is that, as Figure 6 As shown, in this embodiment, a first metal layer 26 for connecting two or more P-type low-doped regions 8 in the terminal area 2 is added in the terminal area 2, and the other parts of the structure are the same as in the first embodiment. This will not be repeated here.

[0059] During the manufacturing process, the first metal layer 26 can be formed at the same time as the first source metal layer 15 and the second source metal layer 21 without adding additional cost.

[0060] In this embodiment, the first metal layer 26 connects two or more P-type low-doped regions 8, so that the connected multiple P-type low-doped regions 8 form an equipotential ring as a whole, which reduces the junction curvature effect and optim...

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Abstract

The invention discloses a super-junction MOS type device with a terminal protection region. A terminal region and a cellular region are sequentially arranged from the edge of the device to the cellular direction of the device, a plurality of mutually independent silicon oxide regions are arranged in the terminal region and the cellular region, P-type doped columns surround the silicon oxide regions, and the depth of the silicon oxide regions is greater than that of the P-type doped columns; the P column is formed on the side surface of the silicon oxide region so that tedious and expensive process steps such as multiple times of photoetching and epitaxial growth are avoided, the cost is saved, and meanwhile, the more flush and uniform P column can be obtained; the silicon oxide regions are deeper than the P-type doped column so that the P-type doped column can be closer to a rectangle; and the P-type low doped region of the terminal region is connected with the adjacent P-type doped column to form an equipotential ring so that the surface electric field of the device is optimized, and the voltage withstanding level of the device is improved. The invention belongs to the technical field of semiconductor power devices, and is suitable for super-junction high-voltage VDMOS devices.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, and relates to a high-voltage VDMOS device, in particular to a super junction MOS device with a terminal protection area. Background technique [0002] As the core electronic components for energy control and conversion in power electronic systems, power semiconductor devices are constantly iteratively updated with the continuous development and in-depth research of semiconductor manufacturing processes. [0003] MOS devices are the most commonly used power semiconductor devices, which have a compromise between forward withstand voltage and on-state voltage drop, that is, increasing the withstand voltage level of the same structure will inevitably lead to an increase in conduction voltage drop, and vice versa. The anticorrelation relationship can be summarized as Ron is positively correlated with V B 2.5 , This is the famous "2.5 times silicon limit". [0004] In order to break t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78
CPCH01L29/0615H01L29/7802
Inventor 廖楠黄武金晓静赵建明夏建新
Owner SICHUAN BLUE COLOR ELECTRONICS TECH