Hardware implementation device of SM3 algorithm

A hardware implementation and algorithm technology, applied in the field of information security, can solve the problems of large hardware area and high cost

Pending Publication Date: 2021-08-24
SPL ELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of this application is to provide a hardware implementation device for the SM3 algorithm to solve the problems of excessive hardware area and high cost when the existing SM3 algorithm is implemented on hardware

Method used

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  • Hardware implementation device of SM3 algorithm
  • Hardware implementation device of SM3 algorithm
  • Hardware implementation device of SM3 algorithm

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Embodiment 1

[0037] The main idea of ​​the present invention is that the device adopts 16 basic message word registers and 3 dynamic message word registers, based on the characteristics of the SM3 algorithm itself: in the calculation of 64 rounds, in the calculation of the 0th round to the 11th round, The 16 basic message word registers are not reassigned. Starting from the 12th round of calculation, the 16 basic message word registers are dynamically assigned. The present invention can realize the SM3 algorithm by using 19 registers, which greatly reduces the hardware based on the SM3 algorithm. area.

[0038] The hardware implementation device of SM3 algorithm, such as figure 1 As shown, it includes an interface module (AHB interface) for receiving the original message data (Message) and outputting the encrypted result (Result), which allows the SM3 module to be mounted on the AHB bus, and the SM3 module can be accessed through the AHB bus;

[0039] Also includes: FIFO storage module fo...

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Abstract

The invention relates to a hardware implementation device of an SM3 algorithm, and belongs to the technical field of information security. The device comprises 16 basic message word registers, which stores 16 initial message words at first, then are operated in 64-round expansion calculation of the SM3 algorithm, wherein the operation comprises 0th-round to 11th-round non-reassignment operation and 12th-round to 63th-round dynamic assignment operation: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in a third dynamic message word register to the last basic message word register; and three dynamic message word registers which are used for dynamically storing message words in each round of expansion calculation and dynamically updating the message words in each round. The device reduces the number of registers, further reduces the area of a hardware device, saves cost and power consumption, and has higher practical engineering application value.

Description

technical field [0001] The invention relates to a hardware realization device of an SM3 algorithm, which belongs to the technical field of information security. Background technique [0002] Hash functions were officially introduced into cryptography in the late 1970s, and were mainly used in message authentication in the early days. It is a one-way cryptographic algorithm, which has the characteristics of compression, simplicity, anti-collision, and anti-collision. These characteristics also make the hash function widely used in the field of cryptography and information security. Commonly used hash functions include SHA-1, SHA-2, MD4, MDS, SM2, and SM3. [0003] The SM3 cryptographic hash algorithm can meet the security requirements of a variety of cryptographic algorithm applications, for example: generate and verify message verification codes through the SM3 hash algorithm, generate digital signatures and verify through the SM3 hash algorithm, and can also provide digita...

Claims

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Application Information

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IPC IPC(8): H04L9/06
CPCH04L9/0631
Inventor 冯炫博张亚国李正卫
Owner SPL ELECTRONICS TECH CO LTD
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