Method and hardware structure capable of realizing convolution calculation in multiple neural networks

A technology of neural network and hardware structure, applied in the direction of biological neural network model, neural architecture, physical realization, etc., can solve the problems of low computing efficiency of traditional CPU, long hardware iteration cycle, huge deployment cost, etc.

Inactive Publication Date: 2021-09-03
井芯微电子技术(天津)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 1. The hardware environment is almost customized, and the support for network upgrades and network changes is poor;
[0007] 2. After the algorithm is updated and the scene changes, the hardware iteration cycle is longer, and the cost is high, and the tape-out risk is greater;
[0008] 3. Traditional CPU has low computing efficiency;
[0009] 4. The energy efficiency ratio of GPU is low, and the deployment cost is huge.

Method used

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  • Method and hardware structure capable of realizing convolution calculation in multiple neural networks
  • Method and hardware structure capable of realizing convolution calculation in multiple neural networks
  • Method and hardware structure capable of realizing convolution calculation in multiple neural networks

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Effect test

Embodiment 1

[0044] Embodiment 1, a method that can realize convolution calculation in various neural networks, by analyzing the convolution operation process in various neural networks, extracting the common features of the convolution calculation change methods involved in the convolution operation process, and The common features are parameterized, and the hardware structure is used to analyze and configure the processed parameters to realize the analysis of different convolution algorithms.

[0045] The basic operations of different CNN networks are roughly the same. The differences are mainly reflected in the different sizes of input feature maps, the number of input feature maps is too different, the dimensions of convolution kernels are different, and the positions of full connections in the network are different. But among the above differences, The process of CNN network operation is composed of convolution, activation, pooling, full connection and other calculation processes; ther...

Embodiment 2

[0069] Embodiment 2 provides a kind of hardware structure (such as figure 1 shown), including: a main control CPU, and a weight cache unit connected to the main control CPU, an input feature map cache unit, an output feature map cache unit, the weight cache unit is used to cache weight data, and the input feature map cache unit , The output feature map cache unit is used to cache feature map data;

[0070] The output end of the weight cache unit is connected to the weight multicast control unit, and the weight multicast control unit is used to broadcast weight data to the parallel computing array unit;

[0071] The output end of the input feature map cache unit is connected to the FP_rd unit, and the output end of the FP_rd unit is connected to the parallel computing array unit;

[0072] The input end of the output feature map cache unit is connected to the Fp_wr unit, and the input end of the Fp_wr unit is connected to the nonlinear computing unit;

[0073] The output end o...

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Abstract

The invention provides a method and a hardware structure capable of realizing convolution calculation in various neural networks, which are characterized in that convolution calculation processes in various neural networks are analyzed, common characteristics of convolution calculation change modes involved in the convolution calculation processes are extracted, parameterization is carried out on the common characteristics. The configured and processed parameters are analyzed by using a hardware structure to realize analysis of different convolution algorithms. According to the method and the hardware structure capable of realizing the convolution calculation in the multiple neural networks, through abstracting multiple convolution neural network calculation processes, network changes are written into a register instruction capable of being analyzed by hardware, and the calculation state of the neural network calculation unit is sensed through the main control CPU; the main control CPU configures weight data, feature map data, a configuration register and other configuration information required by the convolutional neural network calculation unit in real time, and such a hardware structure can realize effective support for various convolutional neural network calculations, and is fast and compatible, and the calculation efficiency is not affected.

Description

technical field [0001] The invention belongs to the technical field of delay performance testing of switching chips, and in particular relates to a method and a hardware structure capable of realizing convolution calculation in various neural networks. Background technique [0002] At present, in the CNN (convolutional neural network) inference acceleration network hardware design, there are mainly the following design directions in the design, lightweight hardware design, low-power hardware design, sparse network hardware design, storage and calculation integrated hardware Design, large computing power hardware design and other directions, each hardware design method has different application scenarios, due to the calculation process of convolutional neural network, the hardware structure is relatively fixed for a certain network, but I want to design a relatively general hardware Environment, to support a variety of convolutional neural network structures, has become relat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/063G06N3/045
Inventor 朱珂王元磊陶常勇汪欣刘长江夏云飞王永胜李晓颖李文强
Owner 井芯微电子技术(天津)有限公司
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