Chip packaging structure and manufacturing method thereof
A technology of chip packaging structure and packaging body, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., and can solve the problem of unstable center of gravity of step structure, difficulty in design, increase of lateral size of chip packaging structure, etc. problem, to achieve the effect of convenient graphic setting, small overall size and accurate electrical connection
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[0029] For a better understanding of the application, various aspects of the application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are descriptions of exemplary embodiments of the application only, and are not intended to limit the scope of the application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.
[0030] It should be noted that in this specification, expressions of first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features. Accordingly, a first fold discussed hereinafter may also be referred to as a second fold without departing from the teachings of the present application. vice versa.
[0031] In the drawings, the thickness, size and shape of comp...
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