Online debugging method for FPGA (Field Programmable Gate Array) with dynamically variable sampling frequency

Abstract

The invention discloses an on-line debugging method for an FPGA (Field Programmable Gate Array) with dynamically variable sampling frequency, and relates to the technical field of FPGAs. According to the method, a user circuit and a monitoring circuit are realized by the FPGA based on a configuration code stream by utilizing programmable logic resources, in the operation process of the user circuit, a clock adjusting module in the monitoring circuit adjusts a sampling clock of a sampling module. the sampling module adopts the corresponding sampling clocks at different time periods to sample the to-be-observed signal to adapt to the running state of the to-be-observed signal, so that on the premise of ensuring that the signal change is monitored, the repeated and unchanged invalid data of sampling is reduced, and the monitoring and debugging efficiency is improved.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an FPGA online debugging method with dynamically variable sampling frequency. Background technique [0002] When the user circuit is implemented on the FPGA and runs normally on the FPGA, in order to ensure that the operation process of the user circuit on the FPGA is correct and conforms to the design idea, it is usually necessary to observe the behavior or waveform of some specific signals inside the user circuit. In order to realize this function, the current method is to add a debugging circuit on the FPGA. When the user circuit is running normally on the FPGA, the debugging circuit is used to sample the signal to be observed of the user circuit and output it to the FPGA for real-time observation and monitoring, and then realize the corresponding debugging. [0003] In actual implementation, the signal to be observed is generally sampled according to a sampling clock and then s...

AI Technical Summary

Problems solved by technology

In many debugging scenarios, some periods of the signal to be observed are critical periods for debugging, and some periods are non-critical periods for debugging. The signal of the signal to be observed hardly changes during the non-critical period, but according to the debugging requirements, it is still necessary to Sampling the signal to be observed during these non-critical periods will result in multiple consecutive samples being the same, and these repeated sampling data are of little significance

Since the monitoring circuit needs to store the sampled data before outputting, the total number of samples in the sampling process is limited by the storage capacity. In the case of limited storage capacity, the total number of samples is also limited. Sampled meaningless data will lead to low debugging efficiency

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