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Multi-sampling-frequency FPGA (Field Programmable Gate Array) online debugging method

A debugging method and multi-sampling technology, applied in the field of FPGA, can solve the problems of limited storage capacity of the total number of samples, little meaning of data, and slow change of the signal to be observed, so as to reduce invalid data with constant sampling repetition and improve efficiency Effect

Active Publication Date: 2021-09-21
WUXI ESIONTECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem with this approach is that some signals to be observed change slowly, and the signal may not change for a long time, so the multiple data continuously sampled by the monitoring circuit are the same, and these repeated sampling data are of little significance
Since the monitoring circuit needs to store the sampled data before outputting, the total number of samples in the sampling process is limited by the storage capacity. In the case of limited storage capacity, the total number of samples is also limited. Sampled meaningless data will lead to low debugging efficiency

Method used

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  • Multi-sampling-frequency FPGA (Field Programmable Gate Array) online debugging method
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  • Multi-sampling-frequency FPGA (Field Programmable Gate Array) online debugging method

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Embodiment Construction

[0024] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0025] The application discloses an FPGA online debugging method with multiple sampling frequencies, and the implementation process of the method is as follows:

[0026] When debugging the user circuit, the configuration code stream corresponding to the global circuit composed of the user circuit and the monitoring circuit is loaded onto the FPGA. The global circuit in this application refers to the entire circuit structure that needs to be implemented using programmable logic resources on the FPGA and run on the FPGA. The global circuit includes at least the user circuit, and the user circuit is the circuit structure used to realize the user-designed function in the global circuit. When debugging the user circuit, the global circuit not only includes the user circuit, but also includes a monitoring circuit connected to the user circuit. The...

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Abstract

The invention discloses a multi-sampling-frequency FPGA (Field Programmable Gate Array) online debugging method, and relates to the technical field of FPGAs. According to the method, an FPGA realizes a user circuit and a monitoring circuit based on a configuration code stream by utilizing a programmable logic resource, in the running process of a user circuit, a plurality of sampling sub-circuits in the monitoring circuit respectively use different sampling clocks to sample a plurality of groups of to-be-observed signals with different signal change speeds of a user circuit, the sampling clocks are matched with control clocks of the to-be-observed signals and are in positive correlation with the control clocks of the to-be-observed signals, the period of the sampling clock is consistent with the expected signal change period of the corresponding to-be-observed signal, so that repeated and unchanged invalid data of sampling can be reduced on the premise of ensuring that the signal change is monitored, and the monitoring and debugging efficiency is improved.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an FPGA online debugging method with multiple sampling frequencies. Background technique [0002] When the user circuit is implemented on the FPGA and runs normally on the FPGA, in order to ensure that the operation process of the user circuit on the FPGA is correct and conforms to the design idea, it is usually necessary to observe the behavior or waveform of some specific signals inside the user circuit. In order to realize this function, the current method is to add a debugging circuit on the FPGA. When the user circuit is running normally on the FPGA, the debugging circuit is used to sample the signal to be observed of the user circuit and output it to the FPGA for real-time observation and monitoring, and then realize the corresponding debugging. [0003] In actual implementation, it is generally necessary to monitor and debug multiple signals to be observed in the user circui...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F1/06
CPCG06F11/2215G06F11/2273G06F1/06
Inventor 单悦尔徐彦峰井站季振凯闫华
Owner WUXI ESIONTECH CO LTD
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