Controllable code pattern data generation device based on fixed sampling rate DAC

Abstract

The invention belongs to the technical field of digital testing, and particularly relates to a controllable code pattern data generation device based on a fixed sampling rate DAC. According to the device, original waveform sampling points are accumulated through a waveform sampling point accumulation module, and the number of waveform sampling points in each clock period is obtained. And real-time calculation is performed on the waveform sampling point of each clock period through an address generation module to obtain address data of the waveform sampling point of each clock period. And the read address is provided for the code pattern data storage module to complete reading of the code pattern data. The mapping module identifies the received code pattern data; a mapping relation between the code pattern data and the voltage data VDn is obtained according to a digital-to-analog conversion relation of the digital-to-analog converter, thus mapping the identified code pattern data through the mapping relation so as to realize voltage data output at any data rate. According to the invention, the limitation of the code pattern data generated by the existing code pattern data synthesis technical scheme in use is overcome.

Description

technical field [0001] The invention belongs to the technical field of digital testing, and in particular relates to a controllable pattern data generating device based on a fixed sampling rate DAC. Background technique [0002] When performing digital system testing, the data generator used as a signal source stimulus needs to generate a huge amount of data of millions or tens of millions. Since the synthetic pattern data generation method based on a digital-to-analog converter (Digital to Analog Converter) has the advantages of flexible signal generation mode and fast data rate switching speed, it has become the most widely used data generation method in the field of digital test technology. [0003] In the synthetic pattern data generation method based on the digital-to-analog converter, there are three commonly used schemes: [0004] One is a scheme based on Direct Digital Waveform Synthesis (DDWS) technology to synthesize pattern data. This scheme is to output waveform...

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Problems solved by technology

However, changing the sampling clock frequency will directly cause the image frequency to change, and the requirements for the low-pass filter will increase, which will directly lead to a greatly increased complexity of the channel conditioning circuit, thereby greatly affecting the quality of the output signal; in addition, because the traditional variable When the clock changes, the clock module needs a period of time to stabilize the clock output, resulting in slow switching speed of the data rate, so that the output signal of this scheme cannot be changed in real time

[0005]The other is the direct digital frequency synthesis technology (Direct Digital Frequency Synthesis, DDFS) synthetic pattern data scheme, in this scheme, its sampling clock is fixed, through The output data rate is changed by changing the frequency control word, but this method also has certain disadvantages. It cannot generate code data with a data rate related to a non-integer multiple of the sampling rate, resulting in a limited data rate of the generated code data; in addition, DDFS It is essentially the extraction of stored waveform data. The larger the frequency control word, the more waveform information will be lost, resulting in serious waveform distortion.

[0006]There is also a memory to directly generate code patterns, such as in FPGA, to generate code pattern data addresses, and send them to the memory with code pattern data inside FPGA to generate directly Code pattern data, in this scheme, the output pattern data level only has high and low levels, that is, "1" and "0" levels, and multi-level pattern data cannot be generated

[0007] It can be seen from the above that no matter what kind of pattern data generation scheme in the prior art, the generated pattern data has certain limitations in use, so It is necessary to improve the existing pattern data generation method

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