Multi-core processor circuit

A processor circuit, multi-core technology, applied in the direction of instruments, simulators, computer control, etc.

Pending Publication Date: 2021-10-19
NUVOTON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional multi-core memory sharing designs require additional cost in the arbiter, especially program memory and data memory

Method used

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  • Multi-core processor circuit
  • Multi-core processor circuit

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Embodiment Construction

[0025] figure 1 It is a schematic diagram of a multi-core processor circuit according to an embodiment of the present invention. Please refer to figure 1 , in this embodiment, the multi-core processor circuit 100 includes a plurality of processor cores 110_1-110_n, a program memory 120, a first bus 130, a data memory 140, a second bus 150, a control circuit 160 and a clock generator 170, wherein the program memory 120 is used to store at least one program instruction INST, and the data memory 140 is used to store at least one program data DATA. Wherein, n is a positive integer greater than or equal to two.

[0026] The first bus bar 130 is coupled between the processor cores 110_1 - 110 — n and the program memory 120 , and the second bus bar 150 is coupled between the processor cores 110_1 - 110 — n and the data memory 140 . The control circuit 160 is coupled to the processor cores 110_1 - 110_n to enable these processor cores 110_1 - 110_n one by one, and disable the rest ...

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PUM

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Abstract

The invention provides a multi-core processor circuit. The multi-core processor circuit comprises a plurality of processor cores, a program memory, a first bus bar, a data memory and a second bus bar. The program memory is used for storing at least one program instruction. The first bus bar is coupled between the processor cores and the program memory. The data memory is used for storing at least one program data. The second bus bar is coupled between the plurality of processor cores and the data memory. The processor cores are enabled one by one to access the program memory and the data memory, and the remaining processor cores are closed.

Description

technical field [0001] The present invention relates to a processor circuit, and in particular to a multi-core processor circuit. Background technique [0002] Thanks to advances in electronics, higher computational complexity can be achieved through the use of multi-core processors. To reduce die cost, a shared memory architecture is often required in multi-core designs. Conventional multi-core memory sharing designs require additional cost in the arbiter, especially program memory and data memory. Therefore, a new architecture is proposed for shared program memory and data memory for multi-core design, so that there is no memory arbiter overhead by using time sharing method. Contents of the invention [0003] The invention provides a multi-core processor circuit, which can omit the overhead of the memory arbiter. [0004] The multi-core processor circuit of the present invention includes a plurality of processor cores, a program memory, a first bus, a data memory and ...

Claims

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Application Information

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IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/25257
Inventor 蔡文浩张宝树谢志明
Owner NUVOTON
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