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Cooperative Circuit Generation Method Based on User Hardware Resource Distribution

A technology of hardware resources and users, applied in electronic circuit testing, integrated circuit testing, electrical measurement, etc., can solve the problems of long error detection time and low reliability evaluation efficiency, and achieve the effect of improving detection efficiency

Active Publication Date: 2022-04-19
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the large scale of the FPGA circuit, the error detection time is long, and the reliability evaluation efficiency is very low.

Method used

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  • Cooperative Circuit Generation Method Based on User Hardware Resource Distribution
  • Cooperative Circuit Generation Method Based on User Hardware Resource Distribution
  • Cooperative Circuit Generation Method Based on User Hardware Resource Distribution

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Experimental program
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Embodiment Construction

[0048] The present invention is described in further detail below in conjunction with specific embodiments, but embodiments of the present invention are not limited thereto.

[0049] from Figure 1 As can be seen, the operation process of this method is to first generate spoke sense code according to resource overhead, and then fuse the user code and spoke sense code to finally generate a synergy code. By adding constraint statements, code fusion is transformed into circuit interleaving. The result is a synergy circuit that can be used for error detection. The concepts in this method are explained in detail below.

[0050] User code: User code refers to the function code that runs on the spacecraft's FPGA device. It is also the code to be protected by this method. Usually the user code is composed of the VHDL language.

[0051] Resources: There are many different kinds of logic units in FPGAs, such as LUT, FF, BRAM, DSP, etc. Different logical units have different roles. These log...

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PUM

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Abstract

The invention belongs to the technical field of FPGA reliability, and in particular relates to a collaborative circuit generation method based on user hardware resource distribution. Including, Step 1: Name the user code resource distribution, name the user code α, and name the submodule code of the user code α i ; The number of FF in each sub-module is Fα i ; The number of LUTs for each sub-module is Lα i ;Step 2: After reducing the distribution of user code resources in step 1 according to the proportional factor, obtain the distribution of code resources of radiation sense; Step 3: according to the distribution of code resources of radiation sense obtained in step 2, generate the code sub-module β of radiation sense i ;Step 4: Convert all submodule codes generated in Step 3 to β i Fusion to form a radiation code β; Step 5: Fusion of the user code α and the radiation code β generated in step 4 to form a code δ, and name it as a collaborative code. The method can estimate the error rate and error position of the user circuit, and can greatly improve the detection efficiency.

Description

Technical field [0001] The present invention belongs to the field of FPGA reliability technology, specifically relates to a collaborative circuit generation method based on the distribution of user hardware resources. Background [0002] In the aerospace field, as a chip with flexible design, low power consumption and high performance, FPGA is widely used in space equipment including deep space exploration and scientific satellites. Because the current FPGA is SRAM type, it is easy to occur single particle flipping, and the current FPGA is developing in the direction of low voltage and high integration, so this makes single particle flipping more likely to occur. When the FPGA is subjected to space radiation, the light makes the equipment work abnormally, and the heavy makes the equipment permanently invalid. Therefore, the single-particle flip can be better evaluated in order to maximize the prevention of the impact of space radiation. [0003] At present, the method of FPGA re...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2868G01R31/287
Inventor 宫江雷闫允一郭宝龙成永盛程首豪
Owner XIDIAN UNIV