Intelligent super-junction MOS device and manufacturing method thereof

Abstract

The invention relates to the field of intelligent super-junction MOS devices, and discloses an intelligent super-junction MOS device and a manufacturing method thereof. According to the invention, the intelligent super-junction MOS device comprises a main MOS and a plurality of functional MOS which are integrally connected on a chip, and the intelligent super-junction MOS device is characterized in that the functional MOS is arranged in the range of the main MOS, the distribution of the functional MOS on the chip comprises a functional MOS isolation region and a functional MOS active region, and the functional MOS active region comprises a plurality of groups of P-type doped region columns and N-type doped region columns which are parallel to each other and are arranged at intervals. The functional MOS isolation region comprises N-type doped region columns and P-type doped region columns, the N-type doped region columns surround the periphery of the functional active region in a square shape, and the P-type doped region columns are evenly distributed in the N-type doped region columns in a lattice shape. According to the intelligent super-junction MOS device disclosed by the invention, the independence of a functional MOS active region can still be ensured after process high-temperature annealing, and ultrahigh isolation voltage can be ensured.

Description

technical field [0001] The invention relates to the field of intelligent super junction MOS devices, more specifically, it relates to an intelligent super junction MOS device and a manufacturing method thereof. Background technique [0002] Intelligent super junction MOS device products are based on ordinary super junction products, integrating sampling MOS, startup MOS, high resistance R, or only integrating one of sampling MOS and startup MOS, ordinary super junction and smart super junction For circuit diagrams, see Figure 13 . It can be seen that the intelligent super-junction MOS device products will have 2 to 3 MOSs on the same chip, and the application circuit requires that the functions of the MOSs are independent and do not affect each other in the working state; [0003] Super junction products are composed of multiple sets of P-type doped region columns and N-type doped region columns alternately connected. Therefore, in the isolation design of sampling MOS and ...

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Problems solved by technology

[0004] Figure 11 and 12 For the super-junction MOS isolation design of the prior art, only the P-type doped region pillars and N-type doped region pillars are arranged in a simple criss-cross arrangement. This design can meet the die withstand voltage requirements, but the isolation between MOS The voltage is less than 10V, and the withstand voltage curve is almost a resistive curve. After analysis, in this design, the active area of ​​sampling MOS and starting MOS is connected to the active area of ​​the main MOS after the process of high-temperature annealing , therefore, there is no real isolation between MOS, so the isolation voltage is very low

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