Analog-to-digital conversion system, clock skew calibration method and related computer program product

Abstract

The invention relates to an analog-to-digital conversion system, a clock skew calibration method and a related computer program product. The analog-to-digital conversion system comprises a multi-stage analog-to-digital conversion unit and a skew calibration circuit. The multi-stage analog-to-digital conversion unit is used for sampling the test signal according to a plurality of staggered clock signals to generate multi-stage quantized outputs. The operation of the multi-stage analog-to-digital conversion unit enables the analog-to-digital conversion system to have a sampling frequency. The test signal has a first frequency, the sampling frequency is N times of the first frequency, and N is an odd number greater than 1. The skew calibration circuit is configured to sequentially analyze the multiple levels of quantized outputs at intervals of N levels to generate a plurality of digital codes. The skew calibration circuit is also configured to calibrate a clock skew of the analog-to-digital conversion system according to a comparison result between the plurality of digital codes and the reference code. According to the invention, a reference circuit which is additionally used as a calibration reference is not needed, and the clock skew can be calibrated by using simple logical operation.

Description

technical field [0001] The disclosed document relates to an analog-to-digital conversion system, in particular to an analog-to-digital conversion system that does not require an additional circuit to provide a calibration reference, a clock skew calibration method, and a related computer program product. Background technique [0002] With the development of various communication technologies and the improvement of hardware specifications, the requirements for the resolution and operation speed of analog-to-digital conversion of signals also increase accordingly. Limited by the process factor, the operation speed of the traditional single-channel ADC has reached the bottleneck of development, so the time-interleaved ADC whose operation speed is directly related to the number of channels has been paid more attention. However, the clock skew error caused by the phase inconsistency of the clock signal is likely to occur among multiple channels of the time-interleaved analog-to-d...

AI Technical Summary

Problems solved by technology

However, it is easy to have clock skew error caused by the phase inconsistency of the clock signal between multiple channels of the time-interleaved analog-to-digital converter, which will seriously affect the performance of the time-interleaved analog-to-digital converter

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