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Memory system and memory access interface device thereof

A memory access and interface device technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problems that cannot meet the speed requirements and cannot meet the use requirements, etc.

Pending Publication Date: 2021-11-05
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the bandwidth requirements of products gradually increase, the traditional single data rate mode architecture can no longer meet the usage requirements and cannot meet the speed requirements

Method used

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  • Memory system and memory access interface device thereof
  • Memory system and memory access interface device thereof
  • Memory system and memory access interface device thereof

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Experimental program
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Embodiment Construction

[0011] An object of the present invention is to provide a memory system and a memory access interface device thereof.

[0012] Please refer to figure 1 . figure 1 A block diagram of a memory system 100 in an embodiment of the present invention is shown. The memory system 100 includes: a memory access controller 110 , a memory access interface device 120 and a storage device 130 .

[0013] The memory system 100 can be electrically coupled to other modules through, for example, but not limited to, a system bus (not shown). For example, the memory system 100 can be electrically coupled to a processor (not shown) through a system bus, so that the processor can access the memory system 100 .

[0014] In one embodiment, the memory access interface device 120 may be, for example, but not limited to, a physical layer circuit. The storage device 130 may be a single data rate (SDR) storage device or a double data rate (DDR) storage device.

[0015] An external access signal, such a...

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PUM

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Abstract

The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

Description

technical field [0001] The invention relates to memory access technology, in particular to a memory system and a memory access interface device. Background technique [0002] NAND flash memory adopts a low-speed single data rate (SDR) mode architecture at the earliest stage. However, as the bandwidth requirements of products gradually increase, the traditional single data rate mode architecture can no longer meet the usage requirements and cannot meet the speed requirements. Therefore, the architecture of non-volatile double data rate (NVDDR) mode is proposed to break through the limitation of speed, and more and more high-speed specifications are proposed under this architecture. [0003] However, the controllers on the market are required to support all speed modes and have the capability of signal correction. Therefore, how to design a new memory access interface device to solve the above defects is an urgent problem in this field. Contents of the invention [0004] ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F13/16
CPCG06F3/061G06F13/1668G06F3/0629G06F3/0679H03K7/08G11C7/222G11C7/1093G11C7/1066G11C11/4076G11C8/18
Inventor 蔡福钦余俊锜张志伟周格至纪国伟陈世昌林士涵蔡旻翰
Owner REALTEK SEMICON CORP