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Reset method, device and apparatus for single board startup timeout and readable storage medium

A technology of a reset device and a reset method, applied in the field of communications, can solve problems such as the inability to switch processors and the inability of single boards to reset automatically.

Pending Publication Date: 2021-11-12
NAT COMP NETWORK & INFORMATION SECURITY MANAGEMENT CENT +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the traditional reset method, during the start-up process of the single board, once the hang-up phenomenon occurs, the watchdog chip still outputs the flag bit signal from the CPLD (programmable logic device) instead of switching to the processor, and then the single-board reset occurs. The phenomenon that the hang cannot be automatically reset

Method used

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  • Reset method, device and apparatus for single board startup timeout and readable storage medium
  • Reset method, device and apparatus for single board startup timeout and readable storage medium
  • Reset method, device and apparatus for single board startup timeout and readable storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] like figure 1 As shown, this embodiment provides a method for resetting a board startup timeout, and the method includes step S1 and step S2.

[0039] Step S1, acquiring a time threshold and first input information, the first input information includes confirmation information that the single board has been powered on and started, and the first input information is used to trigger the programmable logic device on the single board to The hard disk on the single board is used to detect the hard disk action signal;

[0040] Step S2, analyze whether the programmable logic device detects the hard disk action signal within the time threshold, and obtain the analysis result, and the analysis result is used to trigger the reset device to reset the processor in the single board .

[0041] In this embodiment, when the single board is powered on, the programmable logic device (CPLD) will automatically enable the monitoring function of the SATA_ACT (hard disk action) signal, that...

Embodiment 2

[0054] like figure 2 As shown, this embodiment provides a device for resetting a board startup timeout, and the device includes a first acquisition module 701 and a first analysis module 702 .

[0055] The first acquiring module 701 is configured to acquire a time threshold and first input information, the first input information includes confirmation information that the board has been powered on and started, and the first input information is used to trigger The programmable logic device detects the hard disk action signal of the hard disk on the single board;

[0056] The first analysis module 702 is configured to analyze whether the programmable logic device detects the hard disk action signal within the time threshold, and obtain an analysis result, and the analysis result is used to trigger a reset device to reset the single board The processor in the reset operation.

[0057] In the traditional reset method, once the board hangs up during the startup process, the wat...

Embodiment 3

[0067] Corresponding to the above method embodiment, the embodiment of the present disclosure also provides a device for resetting the board startup timeout. The device for resetting the board startup timeout described below and the method for resetting the board startup timeout described above can be referred to in correspondence.

[0068] image 3 It is a block diagram of a device 800 for resetting a board startup timeout according to an exemplary embodiment. like image 3 As shown, the device 800 for resetting the board startup timeout may include: a processor 801 and a memory 802 . The device 800 for resetting the board startup timeout may also include one or more of a multimedia component 803 , an input / output (I / O) interface 804 , and a communication component 805 .

[0069] Wherein, the processor 801 is configured to control the overall operation of the device 800 for resetting the board startup timeout, so as to complete all or part of the steps in the above-mentione...

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PUM

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Abstract

The invention provides a reset method, device and apparatus for starting timeout of a single board and a readable storage medium, and the method comprises the steps: obtaining a time threshold value and first input information which comprises confirmation information that the single board is powered on and started, wherein the first input information is used for triggering a programmable logic device on the single board to carry out hard disk action signal detection on a hard disk on the single board; analyzing whether a programmable logic device detects the hard disk action signal within the time threshold value or not, acquiring an analysis result, wherein the analysis result is used for triggering a reset device to conduct reset operation on a processor in the single board. According to the invention, the programmable logic device is added to monitor the SATAACT signal state of the hard disk of the single board, so that the problem that the single board is hung and cannot be automatically reset in the starting process is solved.

Description

technical field [0001] The present invention relates to the technical field of communication, in particular, to a reset method, device, equipment and a readable storage medium for single-board start-up timeout. Background technique [0002] In the existing communication equipment, especially the reset system of the single-board communication equipment, a watchdog chip is usually used to monitor the operating state of the system. When an error occurs in the system, the watchdog chip will trigger the reset mechanism to reset the processor of the board system and restart the entire system so that the system can run again. In the traditional reset method, during the start-up process of the single board, once the hang-up phenomenon occurs, the watchdog chip still outputs the flag bit signal from the CPLD (programmable logic device) instead of switching to the processor, and then the single-board reset occurs. The phenomenon that the hang cannot be reset automatically. Contents...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07G06F11/14
CPCG06F11/0757G06F11/1441
Inventor 党向磊张良胡燕林李佳云晓春陈训逊吴昊李瑞轩郭庆杰刘慧君李忠志
Owner NAT COMP NETWORK & INFORMATION SECURITY MANAGEMENT CENT
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