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Register data reading optimization method and device and medium

A technology of data reading and optimization methods, which is applied in register devices, machine execution devices, electrical digital data processing, etc., can solve problems such as reducing processor performance and reducing the number of instructions, so as to reduce port conflicts, reduce port conflicts, and improve The effect of utilization

Pending Publication Date: 2021-11-26
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the number of instructions that can be executed in parallel is reduced, reducing processor performance

Method used

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  • Register data reading optimization method and device and medium
  • Register data reading optimization method and device and medium
  • Register data reading optimization method and device and medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0035] Such as figure 1 As shown, the general instruction launch and execution process is as follows: the instruction is fetched, decoded and dispatched, and waits for the operand and execution conditions in the launch queue; then the instruction is selected by the launch selection logic; the selected instruction Read the operand from the register through the shared register port; reach the execution unit corresponding to the instruction to execute the instruction, and write the execution result back to the register. However, in this case, there is still room for optimization due to the fact that the transmit logic is idle and the register port is idle.

[0036] Such as figure 2 As shown, the optimization method for register data reading in this embodiment uses the existing instruction emission logic when the processor contains an operand buffer composed of multiple register values. When no instruction can be issued, the emission logic is idle If the register port is free, ...

Embodiment 2

[0058] This embodiment is basically the same as Embodiment 1, and the main difference is that: in step 3) of this embodiment, different implementations are adopted when putting the read register value into the operand buffer.

[0059] In this embodiment, when the read register value is placed in the operand buffer in step 3), the implementation method adopted is to only store the register data, and pass the number in the operand buffer to the relevant instruction to obtain the data.

[0060] In addition, this embodiment also provides an optimization device for reading register data, including a microprocessor and a memory connected to each other, the microprocessor includes an operand buffer composed of multiple register values, and the microprocessor The register is programmed or configured to perform the steps of the aforementioned optimized method of register data reading.

[0061] In addition, this embodiment also provides a computer-readable storage medium, in which a co...

Embodiment 3

[0063] This embodiment is basically the same as Embodiment 1, and its main differences are:

[0064] In step 4) of this embodiment, different strategies are adopted when transferring the read register information to the selected instruction.

[0065] In this embodiment, when the read register information is delivered to the selected instruction in step 4), the strategy adopted is to use the broadcast path of the result bus to broadcast the read information of the register to all instructions in the launch queue, if any If the register is used by the instruction, then the pointer of the register is pointed to the operand buffer, and the source operand field of the instruction includes an additional bit to indicate whether the operand is acquired in the register or the operand buffer.

[0066] In addition, this embodiment also provides an optimization device for reading register data, including a microprocessor and a memory connected to each other, the microprocessor includes an...

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PUM

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Abstract

The invention discloses a register data reading optimization method and device and a medium, and the register data reading optimization method comprises the following steps: under the condition that a processor comprises an operand buffer consisting of a plurality of register values, transmitting logic by utilizing an existing instruction, and when no instruction can be transmitted and the transmitting logic is idle, if the register port is idle, reading the operand of the instruction from the register to the operand buffer for buffering so as to reduce the conflict probability of the register port and improve the performance of the processor. The invention aims to reduce conflicts caused by port sharing in an out-of-order microprocessor by reading out instruction operands by using idle time accessed by register ports.

Description

technical field [0001] The invention relates to the field of processor microarchitecture, in particular to an optimization method, device and medium for register data reading. Background technique [0002] In order to improve processor performance, current processors generally adopt an out-of-order multiple-issue structure. The out-of-order multiple-issue processor architecture can increase the degree of instruction concurrency, and ultimately increase the number of instructions that can be completed per clock cycle. Increasing the instruction issue width needs to increase related resources on the instruction execution path, such as the number of instruction execution units. Increasing the number of execution components can increase the concurrency of instruction execution and speed up program execution. But there is a price to pay accordingly. First of all, more resources are needed to implement these computing components, and secondly, the corresponding timing will beco...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30003G06F9/30098
Inventor 郑重孙彩霞郭维倪晓强黄立波王俊辉隋兵才雷国庆郭辉邓全王永文
Owner NAT UNIV OF DEFENSE TECH