Register data processing method and device and memory
A data processing and register technology, applied in register devices, electrical digital data processing, machine execution devices, etc., can solve the problems of wasting FPGA interface resources and increasing the development work of the host computer, so as to avoid development work, improve utilization, and save The effect of interface resources
Pending Publication Date: 2021-11-26
ACADEMY OF MILITARY MEDICAL SCI
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[0004] In the prior art, the upper computer is usually connected to the FPGA through a separate transmission channel to read and write control of its register data, but the separate channel will waste the interface resources of the FPGA, and at the same time will increase the development work of the upper computer
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[0058] In order to make the objects, technical solutions, and advantages of the present invention more clearly, the technical solutions in the embodiments of the present invention will be described in contemplation in the embodiment of the present invention. It is an embodiment of the invention, not all of the embodiments. Components of the embodiments of the present invention described and illustrated in the drawings herein can be arranged and design in various configurations.
[0059]Thus, the following detailed description of the embodiments of the invention in the drawings is not intended to limit the scope of the invention claims, but only the selected embodiments of the present invention are shown. Based on the embodiments in the present invention, all other embodiments obtained without creative labor are not made in the premise of creative labor.
[0060] It should be noted that similar reference numerals and letters represent the similar items in the following figures, and...
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The embodiment of the invention provides a register data processing method and device and a memory. The method comprises the steps of after receiving a first data message sent by an upper computer through a business data channel by an FPGA device, analyzing the first data message, and obtaining the register operation information contained in the first data message; and further performing read-write operation on a register according to the register operation information, and sending the read target data to the upper computer, so that the read-write operation on the register data is realized. Compared with the prior art in which the register data processing message is transmitted by a single channel, according to the present invention, the utilization rate of channel resources is improved by multiplexing the channel through the service data and the register operation data, so that the interface resources of the FPGA are saved, and the development work of the upper computer is prevented from being increased.
Description
Technical field [0001] The present invention relates to the field of communications, in particular, to a register data processing method, device, and a memory. Background technique [0002] Currently, Field Programmable Gate Array (FPGA) is widely used in all walks of life, which has the advantages of high programming flexibility, short development cycle, and high parallel computational efficiency. [0003] The internal register function of FPGA is one of the important functions of development and application. Interconnects to other devices, can effectively obtain real information of the reaction device, or control the functionality of the device, and processing the data of the register is usually implemented by connection. . [0004] The prior art upper machine is typically connected to the FPGA through a separate transmission channel to read and write its register data, but a separate channel will waste the FPGA interface resource, which will cause an increase in the developmen...
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Login to View More IPC IPC(8): G06F9/30G06F13/40
CPCG06F9/30141G06F13/4068G06F2213/0026Y02D10/00
Inventor 何昆王娜朱培红吴胜明董方霆李爱玲
Owner ACADEMY OF MILITARY MEDICAL SCI