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Verification method applied to LDPC IP flexible loading double matrixes

A verification method and matrix technology, applied in the storage field, can solve problems such as waste of verification time, achieve the effects of improving verification speed, speeding up the R&D process, and shortening simulation time

Pending Publication Date: 2021-11-30
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Currently, LDPC loads one matrix, which is suitable for one data format, such as 4096; for another data format, such as 520, another matrix needs to be reloaded during verification, and the configuration process is performed from the beginning, which is a waste of verification time

Method used

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  • Verification method applied to LDPC IP flexible loading double matrixes

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Embodiment 1

[0030] This embodiment discloses a verification applied to LDPC IP flexible loading double matrix, such as figure 1 shown, including the following steps:

[0031] S01), passing in the names of matrix 0 and matrix 1 through simulation parameters or compilation parameters;

[0032] Among them, the simulation parameters are applicable to all matrices, and the compilation parameters define several commonly used matrices corresponding to different data formats for different manufacturers' nand models. If the input parameter is 0, the matrix will not be loaded.

[0033] S02), judge the applicable data format of the matrix by the obtained matrix name; for example, matrix 0 is applicable to the data format of 4096, and matrix 1 is applicable to the data format of 520; if matrix 0 is not loaded, then matrix 0 is not applicable to 4096 , also does not apply to 520.

[0034] S03), through the obtained matrix name, use the SystemVerilog system function to obtain the path of the ldpc.h ...

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Abstract

The invention discloses verification applied to LDPC (Low Density Parity Check) IP (Internet Protocol) flexible loading double-matrix, which comprises the following steps of: flexibly selecting and loading different matrixes by simulating or compiling parameters, processing different configuration information defined by the same macro for different matrixes in a configuration process by combining with a SystemVerilog system function. Therefore, manual modification of some configuration parameters of related codes of the loading matrix can be greatly reduced, and the simulation time is shortened.

Description

technical field [0001] The invention relates to the field of storage, in particular to a verification method applied to LDPC IP flexible loading of dual matrices. Background technique [0002] With the advancement of Nand flash technology and the emergence of multi-bit storage technology, the storage density of nand flash has increased significantly, and the bit error rate has also increased sharply. In order to improve the reliability of nand flash, reduce the high bit error rate, the LDPC (Low density Parity Check) code with superior performance and strong error correction capability is proposed. [0003] In the development process of the enterprise-level SSD (solid state disk) master chip, in order to support various nandflash chips on the market, it is necessary to use LDPC codes that support Pairty (parity bits) of various lengths. Therefore, in the development process of LDPC IP, different matrices are needed to adapt to the parity data (parity data) of different nand...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
CPCG06F11/3604G06F11/3684G06F11/3688Y02D30/70
Inventor 夏丽煖姚香君王建利李风志烟晓凤王克涛石易明覃耀
Owner SHANDONG SINOCHIP SEMICON