Wafer alignment method and system, computer readable storage medium and processor

A technology for aligning systems and wafers, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of poor stability of Cu interconnection process and wafer position offset, etc., to improve step coverage and uniformity performance, and the effect of improving stability
CN113725136APending Publication Date: 2021-11-30YANGTZE MEMORY TECH CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
YANGTZE MEMORY TECH CO LTD
Publication Date
2021-11-30

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Abstract

The invention discloses a wafer alignment method and system, a computer readable storage medium and a processor. The method comprises the following steps: acquiring position offset information between a wafer and a bearing assembly; according to the position offset information, determining motion control parameters of a supporting assembly, wherein the supporting assembly is used for separating the wafer from the bearing assembly under a preset condition; and controlling the supporting assembly to move based on the motion control parameter, and driving the wafer to move by the support assembly so as to align the wafer with the bearing assembly. According to the invention, the technical problem of low stability of the Cu interconnection process caused by the deviation of the wafer position in the prior art is solved.
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Description

technical field

[0001] The present invention relates to the technical field of semiconductors, in particular to a wafer alignment method, system, computer readable storage medium and processor. Background technique

[0002] In the Cu interconnection process of the wafer, the wafer is flattened and fixed on the surface of the E-chuck (Electrostatic Adsorption Chuck) by electrostatic adsorption. In order to meet the demand for filling the space towards a small size, a high-temperature reflow process is introduced during the deposition of the seed layer , In the high temperature reflow process, it is necessary to adsorb and release the wafer several times. Since the static electricity of the E-chuck is not completely eliminated when the adsorption is released, it causes incomplete release of the wafer, incomplete release of the wafer and the incomplete release of the wafer. The difference in the warpage of the circle itself will cause a positional shift between the wafer and th...

Claims

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