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Redundancy analysis circuit and memory system including the same

A storage system and circuit technology, applied in the field of storage systems, can solve problems such as poor repair efficiency

Inactive Publication Date: 2021-12-03
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the fixed allocation of redundant word lines or bit lines for PPR operation results in poor repair efficiency

Method used

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  • Redundancy analysis circuit and memory system including the same
  • Redundancy analysis circuit and memory system including the same
  • Redundancy analysis circuit and memory system including the same

Examples

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Embodiment Construction

[0025] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. These examples are provided so that this disclosure will be thorough and complete. References to "one embodiment," "another embodiment," etc. are not necessarily to only one embodiment, and different references to any such phrases are not necessarily to the same embodiment. The term "embodiments" when used herein does not necessarily refer to all embodiments. The presented embodiments are examples only and are not intended to limit the scope of the invention.

[0026] In addition, it should be noted that the terms used herein are only for describing the embodiments, and do not limit the present invention. As used herein, the singular forms are also intended to include the plural unless the context clearly dictates otherwise. It will also be understood that the terms "comprising", "comprising", "comprises" and / or "comprising" when used in this specifica...

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Abstract

The invention relates to a redundancy analysis circuit and a memory system including the same. The memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0064899 filed on May 29, 2020, the entire contents of which are hereby incorporated by reference. technical field [0003] Various embodiments of the present invention relate to a memory system that performs a test operation using a built-in self-test (BIST) circuit and performs a repair operation based on a test result using a built-in redundancy analysis (BIRA) circuit. Background technique [0004] With the development of semiconductor technology, the development of large-capacity, high-performance memory devices is rapidly proceeding. Recently, during mass production of memory devices, defective / faulty cells are repaired by replacing them with spare (redundant) cells in order to satisfy yield and quality. For embedded memory devices used in most systems-on-chip (SoCs), testing and repairing with expensive external test equipment is costly....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/44
CPCG11C29/44G11C29/38G11C29/4401G11C29/76G11C2029/1202G11C2029/1204H01L25/0652H01L25/18H01L2225/06513H01L2225/06541H01L2224/16227H01L2224/13025H01L2224/17181H01L2224/16146H01L2924/15311H01L2924/15192H01L24/16H01L24/17G11C29/18G06F3/0658
Inventor 林在日金头铉金宝拉李圣恩
Owner SK HYNIX INC