Delay-locked loop device and operation method for DLL device

Abstract

The invention provides a delay-locked loop (DLL) device and an operation method for the DLL device. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line delays an input clock in response to a delay code to provide a delayed clock. The replica circuit generates a feedback clock according to the delay clock. The phase detector compares an input clock and a feedback clock to generate a delay control signal. The delay controller generates a delay code at a first point in time according to a delay control signal based on a control clock, and delays a replica delay time length to provide the delay code to the delay line at a second point in time. The delay line adjusts the input clock at a second point in time. The period of the control clock is adjusted to be greater than the replica delay time length.

Description

Technical field [0001] The present invention relates to a delay lock loop apparatus and methods of operating the delay locked loop apparatus, particularly to an arbitrary input clock cycles applied to the delay lock loop apparatus and methods of operating the delay locked loop arrangement. Background technique [0002] In general, the DLL (delay-locked loop, DLL) is a default period set within the received input clock is adjusted to a desired delayed clock. However, in the case where the input clock having a smaller period, the DLL offset excessively occurs frequently (over shift), thereby enabling the delayed clock delayed insufficient or excessive delay situation. In the case where the input clock having a larger cycle, can be improved over the offset DLL, but can not make the DLL received input clock is adjusted to a desired delayed clock period in default. [0003] Therefore, the design is suitable for any input clock cycle delay phase lock loop is one of the topics to those ...

AI Technical Summary

Problems solved by technology

However, in cases where the input clock has a small period, the DLL frequently over-shifts, causing the delayed clock to be under-delayed or over-delayed

In the case of an input clock with a large period, the DLL can improve the excessive skew, but it will make the DLL unable to adjust the received input clock to the desired delayed clock within the default period

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