Separated computing device based on 6T-SRAM

A 6T-SRAM and computing device technology, applied in information storage, static memory, digital memory information, etc., can solve the problem of more single-bit calculations, and achieve the effect of improving calculation accuracy

Active Publication Date: 2021-12-21
中科南京智能技术研究院
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

Traditional storage and calculation chips mostly use voltage or level for calculation, and there are many single-bit calculations

Method used

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  • Separated computing device based on 6T-SRAM
  • Separated computing device based on 6T-SRAM

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Embodiment Construction

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0020] The purpose of the present invention is to provide a separate calculation device based on 6T-SRAM, which improves the accuracy of calculation results.

[0021] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] figure 1 It is a structural schematic diagram...

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Abstract

The invention relates to a separated computing device based on a 6T-SRAM, which comprises a storage and calculation unit array, and is characterized in that the storage and calculation unit array comprises storage and calculation units arranged in a matrix manner; each storage and calculation unit comprises a 6T-SRAM, a transistor M7, a transistor M8 and a capacitor; in each storage and calculation unit, a gate of the transistor M7 is connected with a weight storage point of the 6T-SRAM, a first pole of the transistor M7 is connected with an input signal end, a second pole of the transistor M7 is connected with a first end of the capacitor and a read bit line RBL, a second end of the capacitor is grounded, a gate of the transistor M8 is connected with a control signal end, and both the first pole and the second pole of the transistor M8 are connected with the read bit line RBL; and the read bit lines RBL of the storage and calculation units in each column are connected in a collinear manner. The accuracy of the calculation result is improved.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a separate computing device based on 6T-SRAM. Background technique [0002] Deep Convolutional Neural Networks (DCNNs) are developing rapidly in fields such as artificial intelligence. With its gradual development, more and more issues such as size, efficiency, and energy consumption need to be considered. In the traditional calculation process, the weight is moved between the memory and the operation unit, which does not meet the requirements of low power consumption. In-memory computing (IMC) is increasingly attractive for DCNN acceleration. Traditional storage and calculation chips mostly use voltage or level for calculation, and there are many single-bit calculations. Contents of the invention [0003] The purpose of the present invention is to provide a separate calculation device based on 6T-SRAM, which improves the accuracy of calculation results. [0004]...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/413G11C11/419
CPCG11C11/419G11C11/413
Inventor 乔树山陶皓尚德龙周玉梅
Owner 中科南京智能技术研究院
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