FPGA (Field Programmable Gate Array) wiring method for improving wiring efficiency by utilizing vacant logic resources

Abstract

The invention discloses a field programmable gate array (FPGA) wiring method for improving wiring efficiency by utilizing vacant logic resources, and relates to the field of FPGAs, according to the method, an intervention step is added in a conventional wiring iteration process, for a to-be-processed area which is judged to be difficult to solve a resource conflict problem, a newly-added signal path is formed by the vacant logic resources of the area and is added to a wiring diagram. The input end and the output end do not communicate with each other, that is, the input end and the output end are not communicated with each other on the wiring diagram originally to be converted into wiring resources with communicated paths, so that continuous iteration is unrealistic, the wire net in the candidate area can have more optional paths, resource conflicts are easier to solve, the wiring efficiency is improved, and wiring completion is accelerated.

Description

technical field [0001] The invention relates to the FPGA field, in particular to an FPGA wiring method for improving wiring efficiency by using vacant logic resources. Background technique [0002] FPGA routing is the process of using the programmable interconnect resources of the device to connect the occupied logic units after the chip layout. When routing the FPGA, it is generally necessary to abstract the programmable logic resources on the FPGA including the interconnect resources. Form a wiring diagram with representations of all underlying modules, architecture and interconnection resources on the wiring diagram, then select a signal to be processed in a predetermined order, and find out the source and destination modules related to the signal according to the chip layout results Location, search the wiring diagram with routing algorithms such as congestion negotiation algorithm, find out the unoccupied resources to get a routing path from the source point to the dest...

AI Technical Summary

Problems solved by technology

When the congestion is too high and the number of resource sharing conflicts is large, it may be difficult to separate the lines involved in the resource sharing conflicts because they cannot find unoccupied resources, and the conflicts cannot be eliminated; or due to the slow progress of the congestion negotiation, the operation times out or When the number of iterations reaches the set threshold, routing will fail, and routing takes up a lot of running time in the FPGA application development process. The quality and efficiency of routing directly affect application development efficiency and user experience.

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