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Frame buffer compressor circuit and image processing apparatus

An image processing device and frame buffering technology, applied in image communication, recording signal processing, compressed video signal, etc., can solve the problem of speed reduction

Pending Publication Date: 2022-02-25
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] When the bandwidth increases, the processing capability of the image processing device reaches its limit, which may cause a problem of slowing down in the recording operation or playback (play-back) operation of the video image

Method used

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  • Frame buffer compressor circuit and image processing apparatus
  • Frame buffer compressor circuit and image processing apparatus
  • Frame buffer compressor circuit and image processing apparatus

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Embodiment Construction

[0023] In the following, reference will be made to Figure 1 to Figure 13 Image processing apparatuses according to some example embodiments of the inventive concept are described.

[0024] figure 1 is a block diagram for illustrating an image processing apparatus according to some example embodiments of the inventive concept, figure 2 is for detailed figure 1 Block diagram of the framebuffer compressor.

[0025] refer to figure 1 and figure 2 , The image processing apparatus according to some example embodiments of the inventive concept includes a multimedia IP (intellectual property) (or called a multimedia IP block) 100 , a frame buffer compressor 200 , a memory 300 and / or a system bus 400 .

[0026] The multimedia IP 100 may be a part that directly performs image processing of the image processing device. That is, the multimedia IP 100 may represent various modules for recording images and playing back images such as CAM coding and playback of video images.

[002...

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Abstract

A frame buffer compressor circuit and an image processing apparatus are provided. The image processing apparatus includes a memory configured to store compressed data; and frame buffer compressing circuitry which includes encoder circuitry configured to compress at least some of source data to generate the compressed data and transmit the compressed data to the memory, and decoder circuitry configured to read and decompress the compressed data from the memory, wherein the compressed data includes a payload and a header including actual compressed data and flag, the frame buffer compressing circuitry is configured to reflect a result obtained by comparing an accumulated compressibility corresponding to the compressed data with a reference compressibility in the flag, and is configured to perform compression or decompression in a lossy mode or a lossless mode depending on the flag.

Description

technical field [0001] The inventive concept relates to an image processing apparatus. Background technique [0002] As the demand for video high-resolution images and high frame rate images increases, the amount (ie, bandwidth) of various multimedia IP access memories of image processing devices increases significantly. [0003] When the bandwidth is increased, the processing capability of the image processing device reaches the limit, which may cause a problem of speed reduction at the time of a record operation or a playback (play-back) operation of video images. [0004] Therefore, a type that compresses the size of data when the multimedia IP accesses the memory is being considered. For example, data may be compressed before being written to memory, and the compressed data may be decompressed before being read from memory. Contents of the invention [0005] Aspects of the inventive concepts provide an image processing device having improved image quality and / or reso...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N21/433H04N19/70H04L69/04
CPCH04N21/4331H04N19/70H04L69/04H04N19/124H04N19/15H04N19/46H04N19/176H04N19/172H04N19/91H03M7/607H03M7/3071H04N19/426H04N19/13H04N19/65G11B20/10527G11B20/00007G11B2020/00072
Inventor 李庆九
Owner SAMSUNG ELECTRONICS CO LTD