Non-volatile static random access memory

Abstract

The invention relates to a non-volatile static random access memory. Embodiments of a non-volatile static random access memory (NV-SRAM) cell are disclosed. The NV-SRAM cell includes a static random access memory (SRAM) circuit (e.g., a conventional high performance, high reliability SRAM circuit). However, in order to avoid volatility while still retaining the advantages associated with SRAM circuit operation, the NV-SRAM cell also includes a pair of NVM circuits. The NVM circuits retrieve data values stored on the data nodes of the SRAM circuit prior to power-off, and rewrite the data values back to the data nodes of the SRAM circuit upon power-on. Embodiments of a method of operating selected NV-SRAM cells in a memory array are also disclosed.

Description

technical field [0001] The present invention relates to non-volatile memories, and more particularly to static random access memory (SRAM) circuits configured as non-volatile memories. Background technique [0002] Static Random Access Memory (SRAM) is both a high performance memory (ie, characterized by fast switching speeds) and a high reliability memory (ie, characterized by an extremely low probability of write errors). Furthermore, when SRAMs are powered on, they are considered stable because stored data is retained without any refresh operations. Unfortunately, an obvious disadvantage associated with SRAMs is that they are volatile. In other words, when the SRAM is powered off, the stored data will be lost. Contents of the invention [0003] In view of the above, an embodiment of a non-volatile static random access memory (NV-SRAM) cell is disclosed herein. The NV-SRAM cell may include static random access memory (SRAM) circuitry (eg, conventional high-performance...

AI Technical Summary

Problems solved by technology

Unfortunately, an obvious disadvantage associated with SRAMs is that they are volatile

In other words, when the SRAM is powered off, the stored data will be lost

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