Semiconductor structure and forming method thereof
A semiconductor and patterning technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve problems such as poor device performance, and achieve the effect of improving uniformity and performance
Pending Publication Date: 2022-03-08
SEMICON MFG INT (SHANGHAI) CORP +1
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AI-Extracted Technical Summary
Problems solved by technology
[0004] However, the performance of devices forme...
Method used
[0050] Wherein, in order to reduce the complexity of the process, a selective etching process can be used to remove part of the sidewall of the second fin 121, so that the process of forming a mask on the first fin 111 can be avoided, and the process flow can be simplified. . In the se...
Abstract
The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, forming a first semiconductor layer and a second semiconductor layer which are located in different regions of the substrate on the surface of the substrate, and enabling the first semiconductor layer and the second semiconductor layer to be made of different materials; the first semiconductor layer and the second semiconductor layer are patterned, the first semiconductor layer remaining on the substrate serves as a first fin part, the second semiconductor layer remaining on the substrate serves as a second fin part, and the wall thickness of the first fin part is larger than that of the second fin part; forming a protection layer covering the second fin part; and after the protection layer covering the second fin part is formed, removing part of the side wall of the first fin part, so that the difference between the wall thickness of the first fin part after the part of the side wall is removed and the wall thickness of the second fin part is smaller than or equal to a first preset value. According to the method, the electrical performance of the semiconductor structure is improved.
Application Domain
TransistorSolid-state devices +1
Technology Topic
PhysicsSemiconductor structure +1
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Examples
- Experimental program(1)
Example Embodiment
[0020] Currently formed devices still suffer from poor performance. The reasons for the poor performance of the device are analyzed in conjunction with a method of forming a semiconductor structure.
[0021] refer to figure 1 , shows a schematic structural diagram of a semiconductor structure, including a first fin 1 and a second fin 2, wherein the materials of the first fin 1 and the second fin 2 are different. Usually, in the semiconductor formation process, the first fin 1 and the second fin 2 are formed at the same time, that is, the same patterning process is used, and the first fin and the second fin are formed by dry etching at the same time.
[0022] Traditionally, it is generally believed that the first fin and the second fin formed by the same patterning process have the same size, so little attention has been paid to the problem of size uniformity that may occur in this process.
[0023] However, the inventors of the present invention have found that in the process of forming the first fin and the second fin, the corresponding etching rates are substantially different based on the fact that the first fin and the second fin are made of different materials, As a result, the sizes of the formed first fin and the second fin are different, resulting in poor performance of the device.
[0024] In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the surface of the substrate is formed with a first semiconductor layer and a second semiconductor layer located in different regions of the substrate , the materials of the first semiconductor layer and the second semiconductor layer are different; the first semiconductor layer and the second semiconductor layer are patterned, and the first semiconductor layer remaining on the substrate is the first Fins, using the second semiconductor layer remaining on the substrate as the second fins, the wall thickness of the first fins is greater than the wall thickness of the second fins; forming and covering the second fins a protective layer; removing part of the sidewall of the first fin, so that the difference between the wall thickness of the first fin after removing part of the sidewall and the wall thickness of the second fin is less than or equal to a first preset value .
[0025] It can be seen that in the embodiment of the present invention, after the first fin and the second fin are patterned, a protective layer is formed covering the second fin with a smaller wall thickness, and the protective layer further protects the first fin. Under the premise of two fins, part of the side wall of the first fin is removed, so that the difference between the wall thickness of the first fin after removing part of the side wall and the wall thickness of the second fin is less than or equal to the first fin. A preset value improves the uniformity of the device size and improves the performance of the device.
[0026] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0027] Figure 2 to Figure 10 It is a structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
[0028] refer to figure 2 , providing a substrate 100 , the first semiconductor layer 110 and the second semiconductor layer 120 located in different regions of the substrate 100 are formed on the surface of the substrate 100 .
[0029] The substrate 100 is used as a device base to provide support for device formation, the first semiconductor layer 110 and the second semiconductor layer 120 are used to form fins, the first semiconductor layer 110 and the second semiconductor layer The material of layer 120 is different, so that the first fin and the second fin may be formed with different materials.
[0030] In this embodiment, the material of the substrate 100 may be silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or an on-insulator substrate. Other types of substrates such as germanium substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0031] The material of the first semiconductor layer 110 formed on the surface of the substrate can be materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the second semiconductor layer formed on the surface of the substrate The material of 120 can be materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium. When selecting the materials of the first semiconductor layer 110 and the second semiconductor layer 120, as long as the The materials of the first semiconductor layer 110 and the second semiconductor layer 120 may be different. In this embodiment, the material of the first semiconductor layer 110 formed on the surface of the substrate may be silicon, and the material of the second semiconductor layer 120 formed on the surface of the substrate may be silicon germanium.
[0032] In a specific formation process, the first semiconductor layer 110 and the second semiconductor layer 120 may be formed in different regions of the substrate by using an epitaxial growth process. For example, after blocking the region II for forming the second semiconductor layer, the first semiconductor layer can be formed in the region I for forming the first semiconductor layer, and then, the region for forming the second semiconductor layer II can be exposed, using A second semiconductor layer is formed in the region II where the second semiconductor layer is formed.
[0033] refer to Figure 3 to Figure 4 ,in, image 3 is a sectional view, Figure 4 for top view, image 3 can be understood as Figure 4 In the cross-sectional view along the line AA1, the first semiconductor layer and the second semiconductor layer are patterned, the first semiconductor layer remaining on the substrate is the first fin 111, and the remaining first semiconductor layer on the substrate is The second semiconductor layer on the bottom is the second fin portion 121 , and the wall thickness D1 of the first fin portion 111 is greater than the wall thickness D2 of the second fin portion 121 .
[0034] It can be understood that the materials of the first fin 111 and the second fin 121 are different, and are used to form different types of devices on the same wafer, for example, to form devices with different functions, or to form devices with the same function but different conductivity types ( Such as N-type and P-type) devices.
[0035] In conventional understanding, it is generally considered that the wall thickness D1 of the first fin and the wall thickness D2 of the second fin are equal or nearly equal, however, the inventors of the present invention have found that based on the materials of the first fin and the second fin The difference makes the wall thickness D1 of the first fin and the wall thickness D2 of the second fin not equal, and the gap between the two affects the dimensional uniformity of the device. It can be understood that, based on the different materials of the first semiconductor layer and the second semiconductor layer, the sizes of the first fins and the second fins formed in the same patterning step are substantially different. The embodiment of the invention reduces this difference and improves the dimensional uniformity of the device by providing a corresponding solution.
[0036] On the substrate surface (refer to Figure 4 ), taking the extension direction of the fins (the X direction in the figure) as the first direction, and the direction perpendicular to the extension direction of the fins (the Y direction in the figure) as the second direction, the wall thickness of the fins refers to is the size of the fin along the second direction (Y direction in the figure).
[0037] In the embodiment of the present invention, the fin with a larger wall thickness can be pre-defined as the first fin, and correspondingly, the semiconductor layer used to form the first fin is the first semiconductor layer, and the fin with a smaller wall thickness is the second fin, and correspondingly, the semiconductor layer used to form the second fin is the second semiconductor layer.
[0038]In the embodiment of the present invention, patterning the first semiconductor layer and the second semiconductor layer in this step may include: forming a patterned first mask on the first semiconductor layer and the second semiconductor layer Film layer 130 : using the first mask layer 130 as a mask, etching and removing part of the first semiconductor layer and part of the second semiconductor layer to form a first fin and a second fin.
[0039] Wherein, the first mask layer 130 can be formed by self-aligned double patterning (Self-Aligned Double Patterning, SADP) or self-aligned quadruple patterning (Self-Aligned QuadruplePatterning, SAQP), or this Other craft formations in the field.
[0040] In the process of etching and removing part of the first semiconductor layer and part of the second semiconductor layer, a dry etching process, a wet etching process, or a combination of dry and wet etching processes can be used to achieve, In this embodiment, a part of the first semiconductor layer and a part of the second semiconductor layer may be etched and removed by using a dry etching process, wherein the etching gas used includes Cl 2 and HBr, Cl 2 The flow rate of HBr is 50sccm~1000sccm, the flow rate of HBr is 50sccm~500sccm, the pressure can be 2mτ~100mτ, and the power can be 100W~2000W.
[0041] It should be noted that, in this step, other processes well known in the art may be used to realize the patterning of the first semiconductor layer and the second semiconductor layer. The present invention will not be described in detail here.
[0042] In addition, the first mask layer 130 formed in the patterning process can be retained or removed. In a preferred embodiment of the present invention, the first mask layer 130 is retained so as to protect all the top of the fin.
[0043] refer to Figure 5 to Figure 6 , forming a protective layer covering the second fin.
[0044] The protective layer is used to protect the second fin in the subsequent step of removing part of the sidewall of the first fin, so that the wall thickness of the first fin is similar to the wall thickness of the second fin, thereby improving Uniformity of device size.
[0045] The protective layer may be a layer structure that completely covers the top and sidewalls of the second fin, thereby protecting the second fin.
[0046] In an optional example, the protection layer may be a layer structure covering the top and sidewalls of the second fin and exposing the first fin. Correspondingly, forming the protective layer covering the second fin may include: forming a protective material layer completely covering the sidewalls and tops of the first fin and the second fin; patterning the protective material layer, forming a protection layer exposing the first fin and covering the second fin. Wherein, the protective material layer may be formed through a deposition process, or may be further cured after spin-coating a curable material, and the protective material layer may conformally cover the second fin or completely cover it.
[0047] In the embodiment of the present invention, the patterned first mask layer 130 remains on the second fin 121, so as to protect the top of the second fin 121. This step is preferably on the sidewall of the second fin. The inner wall 141 is formed to further protect the side wall of the second fin, so that the inner wall 141 and the first mask layer 130 are used as the protection layer.
[0048] In order to further reduce the feature size of the fin, in the embodiment of the present invention, when forming the inner wall 141, a part of the side wall of the second fin 121 is removed to form the first indented space 140. In the first indented space 140 forms an inner side wall 141 .
[0049] Specifically, when the patterned first mask layer 130 is formed on the second fin 121, the step of forming the protective layer 141 covering the second fin 121 may include: removing the second Part of the sidewall of the fin forms a first sunken space 140, and the first sunken space 140 is surrounded by the first mask layer 130, the substrate 100 and the remaining sidewalls of the second fin 121 (refer to Figure 5 The part shown by the dotted line box in the center); Form the inner wall 141 in the first sunken space 140 (refer to Image 6 ), using the inner wall 141 and the first mask layer 130 as the protection layer.
[0050] Wherein, in order to reduce process complexity, a selective etching process may be used to remove part of the sidewall of the second fin 121 , thereby avoiding the process of forming a mask on the first fin 111 and simplifying the process flow. In the selective etching process, the selective etching ratio of the second fin 121 to the first fin 111 may be greater than or equal to 10:1.
[0051] Specifically, a dry etching process, a wet etching process, or a combination of dry and wet etching can be used to remove part of the sidewall of the second fin. In the embodiment of the present invention, the dry An etching process removes part of the sidewall of the second fin, wherein the etching gas used includes NF 3 and H 2 , NF 3 The flow rate can be 50sccm ~ 300sccm, H 2 The flow rate can be 50 sccm ~ 2000 sccm.
[0052] After part of the sidewall of the second fin 121 is removed, a first recessed space 140 surrounded by the first mask layer 130 , the substrate 100 and the remaining sidewall of the second fin 121 can be formed. , so that the inner wall 141 can be formed in the first sunken space 140 .
[0053] The forming process of the inner side wall 141 may specifically include: forming a conformal covering on the side of the substrate having the second fin to cover the substrate, the first mask layer and the first recessed space. The sidewall material layer on the top of the substrate and the first mask layer is removed by etching, and the sidewall material layer in the first recessed space is reserved as an inner wall.
[0054] Wherein, the material of the inner wall 141 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride and boron carbonitride , when multiple materials are included, the inner wall may be of laminated structure.
[0055] It can be understood that, in the embodiment of the present invention, removing part of the sidewall of the second fin 141 will further reduce the wall thickness D2 of the second fin, thereby further reducing the feature size of the second fin, Therefore, in the step of patterning the first semiconductor layer and the second semiconductor layer in the embodiment of the present invention, the first fin portion 111 with a larger size can be formed first (the wall thickness of the first fin portion will be thinned in subsequent steps. ) and the second fin portion 121, so that the patterning accuracy requirements of this step are correspondingly reduced, and thus the difficulty of the patterning step is correspondingly reduced.
[0056] refer to Figure 7 After the protective layer covering the second fin is formed, part of the sidewall of the first fin 111 is removed, so that the wall thickness D1 of the first fin 111 after removing part of the sidewall is the same as that of the second fin The difference of the wall thickness D2 of 121 is less than or equal to the first preset value.
[0057] Wherein, the first preset value may be the error range of the characteristic dimensions of the first fin and the second fin, the smaller the first preset value, the corresponding uniformity of the first fin and the second fin the better. In this embodiment, the first preset value is 0-20% of the wall thickness D2 of the second fin in this step, that is, 0-20% of the wall thickness of the second fin after etching. 20%.
[0058] In the embodiment of the present invention, corresponding etching parameters may be determined based on the difference between the wall thicknesses of the first fin and the second fin, so that the wall thicknesses of the first fin and the second fin tend to be the same. Specifically, the step of removing part of the side wall of the first fin includes: determining the difference between the wall thickness of the first fin and the wall thickness of the second fin after part of the side wall is removed, and using the first fin The difference between the wall thickness of a fin and the wall thickness of the second fin is a second preset value; the sidewall of the first fin is removed, and the preset thickness is equal to the second default value.
[0059] Wherein, the difference between the wall thickness of the first fin and the wall thickness of the second fin after removing part of the side wall can be determined by means of spectral measurement, for example, the optical critical dimension (OCD) system is used to realize the measurement of the first fin. The wall thickness and the wall thickness of the second fin are measured, and the difference between the two is further obtained.
[0060] In the step of removing the sidewall of the first fin with a predetermined thickness, a wet etching process, a dry etching process or a combined wet and dry etching process may be used. In this embodiment, a wet etching process may be used to remove the sidewall with a predetermined thickness of the first fin, wherein the etching solution is tetramethylammonium hydroxide (TMAH).
[0061] It should be noted that, based on this embodiment, the materials of the first fin 111 and the substrate 100 are the same, and the etching process may simultaneously remove part of the thickness of the substrate material (not shown in the figure), It can be understood that, based on the effective structure part of the device lies in the fin portion, the substrate will be covered by an isolation layer in a subsequent step to realize the isolation of the substrate and the device, so that even if a part of the thickness of the substrate is removed in this step The material will not affect the formation process of the device.
[0062] In the embodiment of the present invention, after the step of removing part of the sidewall of the first fin, it may further include:
[0063] refer to Figure 8 , removing the inner wall 141 to expose the first sunken space 140;
[0064] After obtaining the first fin part and the second fin part whose wall thickness difference is less than or equal to the first preset value, by removing the inner wall, the first sunken space is exposed, so that the first fin part can be easily removed. The first mask layer exposed by the recessed space.
[0065] Specifically, the inner wall may be removed by wet etching, dry etching, or a combination of wet and dry etching to expose the first recessed space.
[0066] refer to Figure 9 , etching the sidewalls of the first mask layer until the first mask layer exposed at the top of the first recessed space is removed;
[0067] Specifically, it is preferred to use a dry etching process to remove the sidewall of the first mask layer, and in other embodiments, a wet etching process or a combination of dry and wet etching processes may also be used.
[0068] refer to Figure 10 , forming an isolation layer 150 between the first fin portion 111 and the second fin portion 121 .
[0069] By forming an isolation layer between the first fin and the second fin, the subsequent device structure is isolated from the substrate.
[0070] In this embodiment, the step of forming an isolation layer between the first fin and the second fin may include: forming an isolation material layer completely covering the first mask layer; planarizing The isolation material layer, exposing the isolation material layer to the first mask layer; removing the first mask layer; etching back to remove part of the isolation material layer until the first fin and the first fin are exposed. Part of the side wall of the second fin.
[0071]Wherein, a deposition process may be used to form an isolation material layer completely covering the first mask layer. The material of the isolation material layer may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. The isolation material layer may be planarized by a chemical mechanical polishing (CMP) process, and then the first mask layer may be removed by wet etching, dry etching or other etching processes, and after removing the first mask layer, After the mask layer, part of the isolation material layer is etched back to remove part of the sidewalls of the first fin and the second fin, and the remaining isolation material layer is used as an isolation layer.
[0072] In the embodiment of the present invention, after the first fin and the second fin are formed by patterning, a protective layer covering the second fin with a smaller wall thickness is formed, and the second fin is further protected on the protective layer. Under the premise of removing part of the side wall of the first fin, so that the difference between the wall thickness of the first fin after removing part of the side wall and the wall thickness of the second fin is less than or equal to the first preset The value improves the uniformity of the device size and improves the performance of the device.
[0073] In another embodiment of the present invention, a semiconductor structure is further provided, refer to Figure 7 , the semiconductor structure may include:
[0074] The substrate 100; the first fin 111 and the second fin 121 located on the substrate, the materials of the first fin 111 and the second fin 121 are different; for covering the second fin 121 The protective layer; the difference between the wall thickness D1 of the first fin portion 111 and the wall thickness D2 of the second fin portion 121 is less than or equal to a first preset value.
[0075] Wherein, the substrate 100 is used as a base of the device to provide support for the formation of the device. In this embodiment, the material of the substrate 100 may be silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or an on-insulator substrate. Other types of substrates such as germanium substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0076] The material of the first fin 111 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the second fin 121 may be silicon, germanium, silicon germanium, silicon carbide, When materials such as gallium arsenide or gallium indium are selected as materials for the first fin 111 and the second fin 121, as long as the materials of the first fin 111 and the second fin 121 are different, then Can.
[0077] In this embodiment, the material of the first fin 111 may be silicon, and the material of the second fin 121 may be silicon germanium.
[0078] The protective layer may be a layer structure that completely covers the top and sidewalls of the second fin, thereby protecting the second fin. In this embodiment of the present invention, the top of the second fin 121 is provided with a patterned first mask layer 130, so that the top of the second fin 121 can be protected. An inner wall 141 is provided on the side wall, and the inner wall 141 and the first mask layer 130 are used as the protection layer.
[0079] The material of the inner wall 141 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. When multiple materials are included, the inner wall may be of a laminated structure.
[0080] The first preset value may be an error range of the characteristic dimensions of the first fin and the second fin, and the smaller the first preset value, the better the uniformity of the corresponding first fin and the second fin . In this embodiment, the first preset value is 0-20% of the wall thickness D2 of the second fin.
[0081] The semiconductor structure may be formed using the forming methods described in the foregoing embodiments, or may be formed using other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
[0082] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts in each embodiment, refer to each other, that is, Can. As for the device-type embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for related parts, please refer to part of the description of the method embodiments.
[0083] Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.
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