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Automatic system for converting IP module verification information in chip simulation and application

A technology for verifying information and simulation, which is applied in the field of automation systems, can solve problems such as affecting the development cycle, reducing the controllability and observability of chip-level functional verification, and difficulty in creating and maintaining chip-level functional verification platforms, so as to achieve efficient and accurate transplantation , Improve the effect of controllability and observability

Pending Publication Date: 2022-03-11
MOLCHIP TECH (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is no unified standard for the test case conversion of IP modules at present. For different IP modules, verifiers may use different methods when converting test cases (cases), combined with the diversity and complexity of on-chip IP modules This reduces the controllability and observability of chip-level functional verification of IP modules, and makes it more difficult to create and maintain chip-level functional verification platforms.
Therefore, at present, the above-mentioned work is usually performed by senior verification engineers, and the high reliance on manual labor will undoubtedly affect the stability and reliability of the verification platform. Once one or two key personnel cannot work in place, or key personnel make mistakes, it will affect entire development cycle

Method used

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  • Automatic system for converting IP module verification information in chip simulation and application
  • Automatic system for converting IP module verification information in chip simulation and application
  • Automatic system for converting IP module verification information in chip simulation and application

Examples

Experimental program
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Embodiment

[0040] The invention provides an automatic system for converting IP module verification information in chip emulation, comprising an IP module-level UVM verification platform, an SOC chip-level UVM verification platform and a verification information conversion device.

[0041] The IP module-level UVM verification platform uses general verification methodology UVM and System Verilog language to build a verification environment.

[0042] The IP module-level UVM verification platform interacts with the IP module under test through the IP interface signal module, and applies test incentives to the IP module through the written IP module-level test case for functional verification. Specifically, after the design of an IP module is completed, the IP module verifier can manually write a specific test vector casetest according to the module function and interface signal for specific function verification, and write the reference model of the IP module Reference model (or Refmodel ) t...

test example ca

[0043] see figure 1 As shown, the IP module-level UVM verification platform in the embodiment may include a test case case test and the following components: a reference model, an output agent Out_agent, an output agent Out_agent, and a scoreboard. The output agent Out_agent is connected to the Reference model, and the output agent Out_agent is connected to the scoreboard.

[0044] The input agent In_agent is used for the encapsulation and instantiation of the sequencer, driver and monitor. That is, the input agent In_agent includes the encapsulated sequencer, driver and monitor.

[0045] The sequencer is used to manage the sequence generator and generate an effective sequence sequence. Wherein, the sequence generator sequence is used to generate a transaction, and the transaction transaction is used to define a basic item data package.

[0046] The driver is used for applying test stimulus and data conversion to the port of the DUT under test, and the DUT under test is the...

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Abstract

The invention discloses an automatic system for converting IP module verification information in chip simulation and application, and relates to the technical field of chip development. The system comprises an IP module level UVM verification platform, an SOC chip level UVM verification platform and a verification information conversion device, and the verification information conversion device is used for converting connection relation information of a tested IP module and an IP interface signal module. Configuring connection relation information between the tested IP module and the SOC interface signal module by uniformly replacing the IP interface keywords with SOC interface keywords corresponding to the SOC interface signal module; and the component configuration information is added to the SOC chip level UVM verification platform by identifying the component configuration information corresponding to the tested IP module in the IP module level UVM verification platform. According to the invention, the transplantation of the test case can be efficiently and accurately realized, and the controllability and observability of chip-level function verification are improved at the same time.

Description

technical field [0001] The invention relates to the technical field of chip development, in particular to an automatic system and application for converting IP module verification information in chip simulation. Background technique [0002] In the field of IC design, mainstream chip design is increasingly inclined to use reusable IP core (IntellectualProperty core, also known as IP module) SoC (System on Chip, also known as system on chip) design. The speed and quality of the chip are the focus of chip development. In order to ensure the speed and quality of the chip, verifying the IP core of the chip is an important link in the chip development process. [0003] At present, some IP core manufacturers will provide IP cores (verification IP, VIP) for verification, but the provided VIP tools can usually only be used for the verification of the IP cores provided by the manufacturers, and cannot be used for the verification of IP cores of other manufacturers. At the same time,...

Claims

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Application Information

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IPC IPC(8): G06F30/33G06F115/02
CPCG06F30/33G06F2115/02
Inventor 袁力蔡浩胡扬央
Owner MOLCHIP TECH (SHANGHAI) CO LTD