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Compilation optimization method based on cache writing suggestion mechanism

An optimization method and mechanism technology, applied in the field of compilation optimization, can solve problems such as errors in calculation results, and achieve the effects of improving performance, reducing memory access delay, and reducing interference

Pending Publication Date: 2022-03-22
JIANGNAN INST OF COMPUTING TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the actual application subject with complex code structure and large amount of code, manual intervention by the user on the code often introduces some abnormal situations, resulting in errors in calculation results

Method used

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  • Compilation optimization method based on cache writing suggestion mechanism

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Embodiment

[0029] Embodiment: The present invention provides a compilation optimization method based on a cache write hint mechanism, which automatically identifies instruction sequences for writing operations to continuous main memory, and optimizes the memory access behavior of these instruction sequences through instruction insertion, including the following step:

[0030] S1: Identify all write operations in the code and mark them by instrumentation, as follows:

[0031] S11. Traversing the intermediate representation of the code by means of a compilation optimization pass;

[0032] S12. Identify the write operation;

[0033] S13. Use the two instruction chain structures cur_w and cur_w_r to judge the read-after-write of the data unit: if there is a read-after-write correlation to the data unit in the instruction sequence, no subsequent code insertion is performed on the write operation where the data unit is located. Pile, otherwise, go to S14;

[0034] S14. Perform code insertio...

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Abstract

The invention discloses a compilation optimization method based on a cache write hint mechanism, which automatically identifies instruction sequences for performing write operations on continuous main memories, optimizes memory access behaviors of the instruction sequences through instruction instrumentation, and comprises the following steps: S1, identifying all write operations in codes, and marking in an instrumentation mode; s2, judging the access continuity of the data unit of the write operation identified in the step S1, and if a continuity requirement is met, updating a cache instruction parameter; and S3, performing write operation boundary processing. According to the invention, the interference of tedious storage management on the code production process can be reduced, the memory access delay is further reduced, and the performance of the storage system is improved.

Description

technical field [0001] The invention relates to a compilation optimization method based on a cache write hint mechanism, and belongs to the technical field of compilation optimization. Background technique [0002] During the development of electronic computers for more than half a century, Moore's Law indicates that the number of transistors that can be accommodated on an integrated circuit will double every 18 months, that is, the performance of the processor will double every 18 months. . The development of computer system performance increases correspondingly with the development of processor performance, but the performance of application programs is also affected by the storage system. From the perspective of software and hardware, people have adopted a variety of solutions to improve memory access performance, including adding multi-level cache components (such as cache), and management mechanisms for cache components, and so on. [0003] In order to reduce the impa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/41G06F9/50
CPCG06F8/41G06F9/5016
Inventor 朱琪管茂林钱宏吴伟杨涛何王全
Owner JIANGNAN INST OF COMPUTING TECH