System and method for accelerating MMU mapping table deployment

Abstract

The invention provides a system and a method for accelerating MMU mapping table deployment. The system comprises an MMU mapping table generation device and a verification program packaging device which run on a verification program compiling server, and an MMU mapping table deployment device which runs on a target SOC; the MMU mapping table generation device is used for reading, analyzing and legality checking an MMU mapping table configuration file, and generating an MMU mapping table adaptive to the target SOC according to the MMU mapping table configuration file; the verification program packaging device analyzes an original verification program generated by compiling, obtains an MMU mapping table address specified by the verification program and maximum size information of an MMU mapping table, checks validity of the size of the MMU mapping table adapted to a target SOC, and combines and packages the generated MMU mapping table adapted to the SOC and the verification program into a new verification program containing the MMU mapping table; and the MMU mapping table deployment device analyzes the MMU mapping table adapted to the target SOC, and completes deployment of the MMU mapping table on the target SOC.

Description

technical field [0001] The invention relates to the field of SOC chip verification test, in particular to a system and method for accelerating the deployment of an MMU mapping table. Background technique [0002] At present, a considerable part of the verification and testing work in the SOC chip design stage is in the pre-silicon stage, that is, the stage before the chip is returned to the chip, and a large amount of verification work is completed by the verification program (software). [0003] The main verification platforms at this stage are EDA simulation tools, Emulator hardware simulation platforms, etc., whose running speed is very slow compared to real chips; the powerful RichOS cannot meet the verification needs because of the long startup time, so a large number of verification The programs are all bare metal, which makes many functions provided by RichOS unable to be used directly, including the deployment of the memory management unit and the related MMU mapping...

AI Technical Summary

Problems solved by technology

[0003] The main verification platforms at this stage are EDA simulation tools, Emulator hardware simulation platforms, etc., whose running speed is very slow compared to real chips; the powerful RichOS cannot meet the verification needs because of the long startup time, so a large number of verification The programs are all bare metal, which makes many functions provided by RichOS unable to be used directly, including the deployment of the memory management unit and the related MMU mapping table

[0004] If the software verification program does not enable the MMU, the SOC cache cannot be used to speed up the simulation, and the verification time will be very long, and many C library functions cannot be used, resulting in the failure of the verification work; at the same time, because the verification personnel have different divisions of labor, not Every verifier is familiar with the MMU hardware unit of a specific SOC, which makes it difficult for software verifiers who are not familiar with the MMU hardware module to modify the MMU address mapping code, and it is prone to the problem of misconfiguring the MMU, resulting in the failure of verification, or because Incorrect verification result due to incorrect MMU configuration

Images