110 results about "Verification routine" patented technology

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

Systems, apparatuses, methods, and computer program products are disclosed for providing a device trust dashboard. An example method includes generate a device profile for a first user device associated with a user account of a user. The example method further includes determining a device trust score and an authorization rule set for the first user device and updating the device profile for the first user device. The example method further includes receiving a device trust dashboard request and performing a verification routine for the user. The example method further includes providing the device trust dashboard in an instance the user is successfully verified.

A computer implemented system for anonymous electronic verification of location credentials including at least one processor and data storage is described in various embodiments. The system includes cryptographic mechanisms and electronic communication between one or more computing systems that in concert, provide verification of a prover's location credentials in accordance to logical conditions of a verifier's policy without providing additional information to a verifier entity.

According to the kernel indirect control flow transfer dynamic verification method based on the eBPF, an eBPF attachment point of an indirect call instruction is positioned, a verification program is dynamically attached, a source address and a target address are captured to generate a compound key, and the legality of a control flow is verified in a pre-constructed BPF hash table; and meanwhile, three indirect addressing modes of a differential strategy adaptive register, an immediate operand and a memory are adopted. Based on an eBPF technology, an EV program can be dynamically loaded into a running kernel as required during running, and the characteristic of dynamic expansion of a modern kernel can be perfectly adapted; all the capabilities are constructed on a universal software mechanism of a Linux kernel and do not depend on any hardware extension; while powerful security defense is provided, extremely low overhead during operation is realized. Benefited from an innovative hybrid verification strategy and an efficient CFG storage scheme, control flow hijacking attacks in the real world can be effectively defended with extremely low performance loss.

The present invention relates to a leakage detection method for a distribution box, and the technical field of leakage of distribution boxes includes the following steps: S1: real-time acquisition of current signals of each line in the distribution box, using a current transformer or a Hall effect sensor to acquire data; S2: using an adaptive sensitivity adjustment algorithm to automatically adjust the threshold of leakage detection according to real-time environmental parameters and historical data; S3: fast Fourier transform processing of the collected data; S4: when a suspected leakage event is initially detected, a secondary verification procedure is immediately started; S5: after confirming the leakage, the power supply is quickly cut off and an alarm message is sent to a user terminal. The present invention maintains optimal sensitivity and accuracy under different working conditions, avoiding the problem of missed detection or false alarm that may be caused by the traditional fixed threshold method in a complex environment.

The embodiment of the invention provides a program control flow protection method and device based on a shadow stack and computer equipment, and the method comprises the steps that in response to a current calling instruction, at least a return address corresponding to the current calling instruction and a verification value in a verification register are written into the shadow stack, the verification value in the verification register is determined at least based on the return address of the write shadow stack corresponding to the previous call instruction and the verification value; and determining an updated verification value at least based on the return address of the write shadow stack corresponding to the current call instruction and the verification value, and writing the updated verification value into the verification register so as to verify whether the program control flow is normal or not when a current return instruction corresponding to the current call instruction is executed. According to the embodiment of the invention, the protection performance of the program control flow based on the shadow stack can be improved, so that the security of a computer execution program is improved.

To provide a verification apparatus, a verification method, and a verification program that are capable of verifying contents of sentences such as outputs of large language models, which superficially appear to be natural but include false contents, and performing appropriate processing.SOLUTION: A verification apparatus 64 includes: a text selection unit 132 that extracts a verification target portion from an inputted text; a support network creation unit 134 and a contradiction network creation unit 136 that are for collecting, from a set of existing texts, a support text that supports contents of the verification target portion and a contradiction text that contradicts the contents of the verification target portion; and a text editing device 108 that selectively executes, on the basis of whether or not a prescribed relationship is established between the support text and the contradiction text that are collected, processing for maintaining the verification target portion and processing for editing the verification target portion.SELECTED DRAWING: Figure 1

The invention provides an equipment startup verification method and device, electronic equipment, a program product and a medium, and relates to the field of equipment security, the method comprises the following steps: when it is detected that equipment triggers power-on startup, initializing a trusted execution environment of a processor; the firmware program, the bootstrap program and the operating system program serve as programs to be verified in sequence, before the programs to be verified are operated, data to be verified of the programs to be verified are sent to the trusted execution environment, and the data to be verified are verified in the trusted execution environment; wherein the to-be-verified data comprises a signature value, an integrity verification value and a program fragment; if it is determined that the to-be-verified data pass verification, triggering the to-be-verified program to start running; if it is determined that the to-be-verified data does not pass verification, the to-be-verified program is prevented from running; the firmware program, the bootstrap program and the operating system program can be effectively verified in the trusted execution environment, so that the attack of the bootstrap tool can be effectively resisted.

The embodiment of the invention provides a processor chip verification method, a processor chip verification device, electronic equipment, a computer storage medium and a computer program product. The processor chip verification method comprises the following steps: configuring a fetch field of a fetch register as a slice entry address of a slice entry instruction in a verification program, and configuring a permission state field of a permission state register as a slice entry privilege state corresponding to the slice entry instruction; responding to the slice entry privileged state, and sending a memory access request of at least one preorder instruction of the slice entry instruction; sending a jump request of an enabling field of the permission state register so as to enable an instruction fetching field of the instruction fetching register; and when a completion response of the memory access request is received, executing a reading operation for the slice entry address.

A system verifies, utilizing at least a hardware processor, at least one computer-executable instruction of a program using a verification condition. In response to determining that the computer-executable instruction fails the verification condition, the system generates, utilizing at least the hardware processor, a counterexample that comprises an execution trace indicative of a proof failure corresponding to the verification condition. The system generates, utilizing at least the hardware processor, a failing test for debugging the program based on the counterexample.

The present invention provides a model for preoperative verification of a dental treatment plan, a verification tool, a method for manufacturing a verification model, a verification system, and a verification program. The model of the present invention has a model body, a hole specification portion, and a target model portion. A space is formed between the hole specification portion and the target model portion, and the space enables visual confirmation of a range in which a front end of a surgical tool can reach from the hole specification portion toward the target model portion, and enables visual confirmation of a range in which the front end of the surgical tool can reach from the hole specification portion in a tooth arrangement direction and a direction intersecting the tooth arrangement direction.

A device and a method for checking the switchability of an output of a control unit are shown. The method comprises determining that a time has come to execute a test routine, opening a switch connecting a voltage or current source to the output for an initial period of time, measuring the voltage or current output during at least part of the initial period, closing the switch at the end of the initial period, comparing the voltage or current profile measured during the initial period with one or more predetermined criteria that serve as indicators of the switchability of the output, and, if one or more of the predetermined criteria are met, terminating the test routine.a continuation of the verification routine by opening the switch for a second period of time which is longer than the first period of time, a measurement of a voltage or current output during at least part of the second period of time, and a comparison of the voltage or current waveform measured during the second period of time with one or more predetermined criteria which serve as indicators for the switchability of the output.

The present invention discloses an acceleration method and system for Chisel bounded model checking based on control flow and data flow information, belonging to the field of formal verification of hardware design. The method includes: compiling the program to be verified to obtain the FIRRTL intermediate representation during the compilation process and the FIRRTL abstract syntax tree of the program to be verified; obtaining the branch structure information of the program to be verified according to the FIRRTL abstract syntax tree; combining the FIRRTL abstract syntax tree to perform assertion-based slicing on the program to be verified and retain the FIRRTL intermediate representation related to the assertion; generating a transition system S based on the FIRRTL intermediate representation related to the assertion; and performing detection on the program to be verified based on the transition system S and the branch structure information. The present invention can accelerate the BMC verification process of the hardware design generated by Chisel by utilizing the control flow and data flow information in the program.

Computer-implemented method, including: Receiving a validation request in a vehicle data processing system (VCS) from a paired wireless device; Receiving facility identification information from the wireless facility; Validating the identity of the wireless device; and Sending vehicle identification information and payment-related information to the wireless device in response to validation of the wireless device's identity.

A verification device according to an embodiment includes a first determination unit and a second determination unit. The first determination unit determines whether a regular expression follows a syntax (for example, a syntax of a regular expression according to the Backus-Naur form) designated in advance. The second determination unit determines whether a condition (for example, real-world strong 1-unambiguity (RWS1U)) indicating that the processing time when the regular expression analyzes a character string is linear with respect to the length of the character string is satisfied.

The invention provides a program verification case construction method and device, a storage medium and equipment. The method comprises the following steps: acquiring a program code of a program to be verified; wherein the program code comprises a plurality of program units; according to the input value and the return value of each program unit, determining a calling relationship between the program units, and generating a program calling sequence according to the calling relationship, the program calling sequence comprising at least two program units having the calling relationship in the program codes; inputting the program calling sequence into a preset use case generation model, and generating a reconstruction code based on the code reconstruction prompt information by using the use case generation model; and inputting the reconstruction code into a use case generation model, and generating a verification use case for the to-be-verified program by using the use case generation model based on the use case generation prompt information. According to the scheme, the coverage rate of the verification case on the function statements in the to-be-verified program is increased, and the reliability of the verification case is improved.

The application discloses a bus-driven chip simulation excitation model for IP unit level verification, which is realized through the following processes: S1, replacing an IO register access sequence of a system software driver; S2, replacing a register timing sequence guarantee function of the driver; and S3, replacing a test excitation initialization process of a test machine, and directly calling a verification program entrance of the system software.

The present application relates to a method for verifying the trust level of a system program based on an edge Internet of Things proxy device, including the following specific steps: Considering the characteristic that the one-time programmable memory eFuse can only be programmed once, the hash value of the secure root key SRK based on the eFuse characteristic is burned in and used as the root of trust; Starting from the boot of the operating system, multi-level verification is carried out until the trust level verification program for boot-up is completed to ensure the security of the boot of the operating system. Based on the premise of being granted credit by the "trust level verification program", the present application verifies the trust levels of the system's built-in application programs and newly added application programs later, eliminating the risk that the traditional "whitelist" protection mechanism loses its protection effectiveness due to the uncontrollability of the secure boot of the operating system, and fundamentally solving the trust problem of the programs running within the system.

The invention discloses a verification method and device of a performance simulator, equipment, a medium and a program product, and belongs to the field of chip verification. The method comprises the steps that a universal verification program is called, and the universal verification program serves as a class file to support execution of object-oriented instantiation operation and supports parameter specifying through a configuration file and is used for obtaining a verification program of a performance simulator of each subsystem in the system on chip; when object-oriented instantiation operation is executed on the general verification program, parameters of a first performance simulator are injected through the configuration file, a first verification program corresponding to the first performance simulator is obtained, and the first performance simulator is a performance simulator in any subsystem in the system on chip; a verification process for the first performance simulator is performed by the first verification program. The invention provides a universal verification method for a performance simulator.

The invention relates to a computer-implemented method for operating a code generator for creating and implementing verified program code for calculating a neural network on a hardware environment (2) comprising the following steps: - Creating (S1) program code for calculating a neural network in a hardware environment based on a defined neural network; - Providing (S2) the created program code with a verification code, wherein the verification code, upon execution, checks the execution of the program code in the hardware environment (2) against at least one verification criterion; - Implementing and executing (S3) the program code provided with the verification code in the hardware environment (2); - Upon finding that the at least one verification criterion is met, creating (S5) the program code without the verification code; - Implementing (S6) the program code without the verification code in the hardware environment (2).

The present invention discloses a counter-example guided sparse spatial flow model detection method and system, compiles the C program code to be verified into LLVM intermediate code; constructs a sparse spatial flow model of the program to be verified; abstracts the model variables, and executes a model detection algorithm of explicit value analysis to detect whether there are counter-examples in the abstract model; verifies the feasibility of the counter-examples, and determines whether the counter-example path is valid in the original model; guides the model to refine the abstraction based on interpolation and the path, context and field sensitive strong update refinement model through counter-example information, and performs model detection again; determines whether the program violates the security attribute by the presence or absence of weak updates on the counter-examples and counter-example paths. The method of the present invention can accurately and efficiently analyze the state changes of C language program software at the symbol level and address space level by implementing the counter-example guided sparse spatial flow model detection method, and realizes security formal verification.

To properly realize a byte code injection attack by malware.SOLUTION: A byte code injection processing unit 130 of a verification device 100 writes malicious byte code to a memory address where target byte code has been located. A symbol table search unit 141 repeatedly performs pointer detection through memory searches and calculation of a start address of a structure based on the structure information of a symbol table, thereby calculating a start address of a management structure that manages the execution state of a script and function information. A symbol table injection unit 142 writes a malicious symbol table to an address identified from the start address of the management structure calculated by the symbol table search unit 141. An execution processing unit 120, with respect to malicious byte code and a malicious symbol table written into a memory space of a process of a temporarily stopped script engine, restarts the process of the script engine so as to execute the malicious byte code while referring to the malicious symbol table.SELECTED DRAWING: Figure 2

The invention discloses a verification method and device based on a shader compiler and a storage medium, and relates to the field of program detection.The verification method comprises the steps that a front-end compiler of a target shader is called to convert a to-be-verified program into an intermediate statement; determining a first instruction set executed by a central processing unit and a second instruction set executed by a graphics processor according to the intermediate statement; obtaining a first result set obtained by executing the first instruction set by the central processing unit; executing the second instruction set through a simulation back-end compiler to obtain a second result set; and verifying the second result set according to the first result set to obtain a verification result. Therefore, on the premise that a rear-end editor of an entity graphics processor is not used, various types of simulation rear-end compilers are used for verifying the to-be-verified program, and verification cost is reduced. Automatic verification of the second result obtained by the simulation back-end compiler can be realized, and the verification efficiency of the to-be-verified program is improved.

A verification apparatus for verifying an ID card is provided. The verification apparatus includes a processor configured to acquire, as a second captured image, an image obtained by capturing a verification image printed on an ID card to be verified, acquire, from a memory, a first captured image obtained by capturing the verification image and stored in the memory, and verify authenticity of the ID card to be verified by comparing density characteristics of each of the first captured image and the second captured image.

Embodiments of the present application provide a computer target object verification method, device, storage medium and related device. The computer target object verification method comprises: obtaining a public key signature, wherein the public key signature comprises a signature of a processor private key on a public key certificate, and the public key certificate comprises at least a computer public key; using a processor public key pre-configured in the processor to verify the public key signature; when the processor public key verifies the public key signature successfully, using the computer public key to verify a target signature, wherein the target signature is a signature of a computer private key on a target object; and when the computer public key verifies the target signature successfully, the target object is verified successfully. It can be seen that the computer target object verification method provided by the embodiments of the present application can be implemented by a computer while verifying the trusted root verification program or data in the processor.

The utility model provides a system for burning and reading verification chips in parallel. The system comprises a software module and at least one hardware module. The hardware module comprises a plug connector, a burning port and a burner; the software module comprises an upper computer, and the upper computer is connected with the burner and an LIN pin of the male end of the plug connector; the upper computer comprises a burning program and a reading verification program, the burning program is used for burning the target module through the burner, and the reading verification program is used for checking data in real time through the LIN port to judge whether the target module is successfully burnt or not. According to the utility model, the chip is read and verified while program burning is carried out on the chip in the same time period, so that the production efficiency and the verification accuracy can be obviously improved.

An embodiment of the present invention discloses a method for building a verification environment for SOC simulation verification and an SOC simulation verification device. The SOC simulation verification method includes: loading a bootloader; wherein, the bootloader has transplanted the drivers of the minimum system device modules of the SOC in the simulation verification device; loading an operating system; wherein, the operating system has transplanted the drivers of the minimum system device modules of the SOC in the simulation verification device; when starting the operating system through the bootloader, remotely connecting to a network file system through the operating system; when receiving at least one verification instruction for other device modules of the SOC except for the minimum system device modules, loading a verification program file matching the verification instruction from the network file system, and running the verification program file to perform verification tests on other device modules of the SOC, which can shorten the time for loading the verification program file, support multi-user parallel verification, improve the verification test efficiency, and support system-level combined verification.

In some aspects, a method is provided that includes, for example, performing, by a verifier entity, at least one secondary task using at least one result indicated in at least received information; a tag for at least one radio signal measurement associated with the at least one result is determined by the verifier entity and using at least one output of the at least one auxiliary task, or a tag for at least one radio signal measurement associated with the at least one result is determined by the verifier entity and based on the at least one output of the at least one auxiliary task. Determining that at least one radio signal measurement associated with the at least one result is to be discarded; and transmitting the tag and the at least one radio signal measurement to the first network node or the second network node to update the machine learning model for the primary task.

The invention discloses a complex program verification method based on nonlinear constraint local search solution, which belongs to the technical field of computer program verification, and comprises the following steps: generating an SMT-NRA formula of a program to be verified based on a verification target; constructing a linear equation set based on linear equality constraints in the formula, and performing replacement from non-free variables to free variables by solving the equation set to obtain a simplified formula; heuristic initialization based on a divide-and-conquer strategy is carried out on the simplified formula; an initial assignment value is obtained through standard random initialization and short-time search solution, or local search solution is carried out by dividing sub-formulas; performing iterative search on the initial assignment based on multi-path parallelism and adaptive neighborhood limitation; maintaining a multi-path list, adaptively determining candidate moving directions in each round, and allocating the candidate moving directions to each path to update the assignment; and judging the property of the to-be-verified program according to a final result of the iterative search and outputting a conclusion. According to the invention, efficient verification of the key program module containing complex nonlinear logic is realized.