95 results about "Verification routine" patented technology

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

According to the kernel indirect control flow transfer dynamic verification method based on the eBPF, an eBPF attachment point of an indirect call instruction is positioned, a verification program is dynamically attached, a source address and a target address are captured to generate a compound key, and the legality of a control flow is verified in a pre-constructed BPF hash table; and meanwhile, three indirect addressing modes of a differential strategy adaptive register, an immediate operand and a memory are adopted. Based on an eBPF technology, an EV program can be dynamically loaded into a running kernel as required during running, and the characteristic of dynamic expansion of a modern kernel can be perfectly adapted; all the capabilities are constructed on a universal software mechanism of a Linux kernel and do not depend on any hardware extension; while powerful security defense is provided, extremely low overhead during operation is realized. Benefited from an innovative hybrid verification strategy and an efficient CFG storage scheme, control flow hijacking attacks in the real world can be effectively defended with extremely low performance loss.

The embodiment of the invention provides a program control flow protection method and device based on a shadow stack and computer equipment, and the method comprises the steps that in response to a current calling instruction, at least a return address corresponding to the current calling instruction and a verification value in a verification register are written into the shadow stack, the verification value in the verification register is determined at least based on the return address of the write shadow stack corresponding to the previous call instruction and the verification value; and determining an updated verification value at least based on the return address of the write shadow stack corresponding to the current call instruction and the verification value, and writing the updated verification value into the verification register so as to verify whether the program control flow is normal or not when a current return instruction corresponding to the current call instruction is executed. According to the embodiment of the invention, the protection performance of the program control flow based on the shadow stack can be improved, so that the security of a computer execution program is improved.

A system verifies, utilizing at least a hardware processor, at least one computer-executable instruction of a program using a verification condition. In response to determining that the computer-executable instruction fails the verification condition, the system generates, utilizing at least the hardware processor, a counterexample that comprises an execution trace indicative of a proof failure corresponding to the verification condition. The system generates, utilizing at least the hardware processor, a failing test for debugging the program based on the counterexample.

The present invention provides a model for preoperative verification of a dental treatment plan, a verification tool, a method for manufacturing a verification model, a verification system, and a verification program. The model of the present invention has a model body, a hole specification portion, and a target model portion. A space is formed between the hole specification portion and the target model portion, and the space enables visual confirmation of a range in which a front end of a surgical tool can reach from the hole specification portion toward the target model portion, and enables visual confirmation of a range in which the front end of the surgical tool can reach from the hole specification portion in a tooth arrangement direction and a direction intersecting the tooth arrangement direction.

A device and a method for checking the switchability of an output of a control unit are shown. The method comprises determining that a time has come to execute a test routine, opening a switch connecting a voltage or current source to the output for an initial period of time, measuring the voltage or current output during at least part of the initial period, closing the switch at the end of the initial period, comparing the voltage or current profile measured during the initial period with one or more predetermined criteria that serve as indicators of the switchability of the output, and, if one or more of the predetermined criteria are met, terminating the test routine.a continuation of the verification routine by opening the switch for a second period of time which is longer than the first period of time, a measurement of a voltage or current output during at least part of the second period of time, and a comparison of the voltage or current waveform measured during the second period of time with one or more predetermined criteria which serve as indicators for the switchability of the output.

The present invention discloses an acceleration method and system for Chisel bounded model checking based on control flow and data flow information, belonging to the field of formal verification of hardware design. The method includes: compiling the program to be verified to obtain the FIRRTL intermediate representation during the compilation process and the FIRRTL abstract syntax tree of the program to be verified; obtaining the branch structure information of the program to be verified according to the FIRRTL abstract syntax tree; combining the FIRRTL abstract syntax tree to perform assertion-based slicing on the program to be verified and retain the FIRRTL intermediate representation related to the assertion; generating a transition system S based on the FIRRTL intermediate representation related to the assertion; and performing detection on the program to be verified based on the transition system S and the branch structure information. The present invention can accelerate the BMC verification process of the hardware design generated by Chisel by utilizing the control flow and data flow information in the program.

Computer-implemented method, including: Receiving a validation request in a vehicle data processing system (VCS) from a paired wireless device; Receiving facility identification information from the wireless facility; Validating the identity of the wireless device; and Sending vehicle identification information and payment-related information to the wireless device in response to validation of the wireless device's identity.

A verification device according to an embodiment includes a first determination unit and a second determination unit. The first determination unit determines whether a regular expression follows a syntax (for example, a syntax of a regular expression according to the Backus-Naur form) designated in advance. The second determination unit determines whether a condition (for example, real-world strong 1-unambiguity (RWS1U)) indicating that the processing time when the regular expression analyzes a character string is linear with respect to the length of the character string is satisfied.

The invention provides a program verification case construction method and device, a storage medium and equipment. The method comprises the following steps: acquiring a program code of a program to be verified; wherein the program code comprises a plurality of program units; according to the input value and the return value of each program unit, determining a calling relationship between the program units, and generating a program calling sequence according to the calling relationship, the program calling sequence comprising at least two program units having the calling relationship in the program codes; inputting the program calling sequence into a preset use case generation model, and generating a reconstruction code based on the code reconstruction prompt information by using the use case generation model; and inputting the reconstruction code into a use case generation model, and generating a verification use case for the to-be-verified program by using the use case generation model based on the use case generation prompt information. According to the scheme, the coverage rate of the verification case on the function statements in the to-be-verified program is increased, and the reliability of the verification case is improved.

The application discloses a bus-driven chip simulation excitation model for IP unit level verification, which is realized through the following processes: S1, replacing an IO register access sequence of a system software driver; S2, replacing a register timing sequence guarantee function of the driver; and S3, replacing a test excitation initialization process of a test machine, and directly calling a verification program entrance of the system software.

The present application relates to a method for verifying the trust level of a system program based on an edge Internet of Things proxy device, including the following specific steps: Considering the characteristic that the one-time programmable memory eFuse can only be programmed once, the hash value of the secure root key SRK based on the eFuse characteristic is burned in and used as the root of trust; Starting from the boot of the operating system, multi-level verification is carried out until the trust level verification program for boot-up is completed to ensure the security of the boot of the operating system. Based on the premise of being granted credit by the "trust level verification program", the present application verifies the trust levels of the system's built-in application programs and newly added application programs later, eliminating the risk that the traditional "whitelist" protection mechanism loses its protection effectiveness due to the uncontrollability of the secure boot of the operating system, and fundamentally solving the trust problem of the programs running within the system.

The invention discloses a verification method and device of a performance simulator, equipment, a medium and a program product, and belongs to the field of chip verification. The method comprises the steps that a universal verification program is called, and the universal verification program serves as a class file to support execution of object-oriented instantiation operation and supports parameter specifying through a configuration file and is used for obtaining a verification program of a performance simulator of each subsystem in the system on chip; when object-oriented instantiation operation is executed on the general verification program, parameters of a first performance simulator are injected through the configuration file, a first verification program corresponding to the first performance simulator is obtained, and the first performance simulator is a performance simulator in any subsystem in the system on chip; a verification process for the first performance simulator is performed by the first verification program. The invention provides a universal verification method for a performance simulator.

The invention relates to a computer-implemented method for operating a code generator for creating and implementing verified program code for calculating a neural network on a hardware environment (2) comprising the following steps: - Creating (S1) program code for calculating a neural network in a hardware environment based on a defined neural network; - Providing (S2) the created program code with a verification code, wherein the verification code, upon execution, checks the execution of the program code in the hardware environment (2) against at least one verification criterion; - Implementing and executing (S3) the program code provided with the verification code in the hardware environment (2); - Upon finding that the at least one verification criterion is met, creating (S5) the program code without the verification code; - Implementing (S6) the program code without the verification code in the hardware environment (2).

The invention discloses a verification method and device based on a shader compiler and a storage medium, and relates to the field of program detection.The verification method comprises the steps that a front-end compiler of a target shader is called to convert a to-be-verified program into an intermediate statement; determining a first instruction set executed by a central processing unit and a second instruction set executed by a graphics processor according to the intermediate statement; obtaining a first result set obtained by executing the first instruction set by the central processing unit; executing the second instruction set through a simulation back-end compiler to obtain a second result set; and verifying the second result set according to the first result set to obtain a verification result. Therefore, on the premise that a rear-end editor of an entity graphics processor is not used, various types of simulation rear-end compilers are used for verifying the to-be-verified program, and verification cost is reduced. Automatic verification of the second result obtained by the simulation back-end compiler can be realized, and the verification efficiency of the to-be-verified program is improved.

A verification apparatus for verifying an ID card is provided. The verification apparatus includes a processor configured to acquire, as a second captured image, an image obtained by capturing a verification image printed on an ID card to be verified, acquire, from a memory, a first captured image obtained by capturing the verification image and stored in the memory, and verify authenticity of the ID card to be verified by comparing density characteristics of each of the first captured image and the second captured image.

Embodiments of the present application provide a computer target object verification method, device, storage medium and related device. The computer target object verification method comprises: obtaining a public key signature, wherein the public key signature comprises a signature of a processor private key on a public key certificate, and the public key certificate comprises at least a computer public key; using a processor public key pre-configured in the processor to verify the public key signature; when the processor public key verifies the public key signature successfully, using the computer public key to verify a target signature, wherein the target signature is a signature of a computer private key on a target object; and when the computer public key verifies the target signature successfully, the target object is verified successfully. It can be seen that the computer target object verification method provided by the embodiments of the present application can be implemented by a computer while verifying the trusted root verification program or data in the processor.

The utility model provides a system for burning and reading verification chips in parallel. The system comprises a software module and at least one hardware module. The hardware module comprises a plug connector, a burning port and a burner; the software module comprises an upper computer, and the upper computer is connected with the burner and an LIN pin of the male end of the plug connector; the upper computer comprises a burning program and a reading verification program, the burning program is used for burning the target module through the burner, and the reading verification program is used for checking data in real time through the LIN port to judge whether the target module is successfully burnt or not. According to the utility model, the chip is read and verified while program burning is carried out on the chip in the same time period, so that the production efficiency and the verification accuracy can be obviously improved.

An embodiment of the present invention discloses a method for building a verification environment for SOC simulation verification and an SOC simulation verification device. The SOC simulation verification method includes: loading a bootloader; wherein, the bootloader has transplanted the drivers of the minimum system device modules of the SOC in the simulation verification device; loading an operating system; wherein, the operating system has transplanted the drivers of the minimum system device modules of the SOC in the simulation verification device; when starting the operating system through the bootloader, remotely connecting to a network file system through the operating system; when receiving at least one verification instruction for other device modules of the SOC except for the minimum system device modules, loading a verification program file matching the verification instruction from the network file system, and running the verification program file to perform verification tests on other device modules of the SOC, which can shorten the time for loading the verification program file, support multi-user parallel verification, improve the verification test efficiency, and support system-level combined verification.

The invention discloses a complex program verification method based on nonlinear constraint local search solution, which belongs to the technical field of computer program verification, and comprises the following steps: generating an SMT-NRA formula of a program to be verified based on a verification target; constructing a linear equation set based on linear equality constraints in the formula, and performing replacement from non-free variables to free variables by solving the equation set to obtain a simplified formula; heuristic initialization based on a divide-and-conquer strategy is carried out on the simplified formula; an initial assignment value is obtained through standard random initialization and short-time search solution, or local search solution is carried out by dividing sub-formulas; performing iterative search on the initial assignment based on multi-path parallelism and adaptive neighborhood limitation; maintaining a multi-path list, adaptively determining candidate moving directions in each round, and allocating the candidate moving directions to each path to update the assignment; and judging the property of the to-be-verified program according to a final result of the iterative search and outputting a conclusion. According to the invention, efficient verification of the key program module containing complex nonlinear logic is realized.

This application relates to an air conditioning unit motherboard, a universal display board, and a verification method for the display board. The method applied to the display board includes: sequentially initiating verification to each stored unit application program through a verification program; obtaining communication data fed back by each unit application program; sequentially sending the communication data to the air conditioning unit motherboard; obtaining a response from the air conditioning unit motherboard; determining the communication data and unit application program corresponding to the response; and waking up the unit application program corresponding to the response. In this application, only the verification program and the unit application programs corresponding to each model need to be pre-stored in the display board. The verification program can then determine the unit application program corresponding to the air conditioning unit motherboard to be matched, thus completing the functional control of the air conditioning unit motherboard to be matched. The technical solution in this application allows the same display board to be adapted to air conditioning unit motherboards of different models, thereby improving the efficiency of the entire R&D lifecycle.

The present application discloses an interface verification method, an electronic device, a storage medium, and a program product, relating to the technical field of servers. After starting the firmware interface of the server, an interface verification program is imported into the firmware interface, and the command-line interface of the firmware interface is set to have access rights to the interface verification program. The interface verification program is run on the command-line interface of the firmware interface to verify the reliability of the target keyboard controller style interface, and a reliability verification result of the target keyboard controller style interface is obtained. Without booting the operating system, the reliability verification of the keyboard controller style interface can be implemented on the command-line interface of the firmware interface after the firmware interface is started, solving the technical problems in the related art of relatively strict requirements for the hardware environment and long verification waiting time, and achieving the technical effects of reducing the dependence on the hardware environment and shortening the verification waiting time.

The application discloses a program verification metadata export method and device and a deterministic execution environment, and belongs to the field of compiling technology and formal verification. The method comprises the following steps: marking the pointer ownership state in the source code through attribute annotation; extracting the ownership conversion information and generating the structured metadata during compiling; and outputting the metadata to the special section of the compiling product, so that the memory safety of the program can be verified independently by directly reading the metadata by an external system. In order to make the exported metadata complete and inferable, a deterministic running environment composed of zero global state context, full-link memory management, capability token and deterministic execution suite is provided. In the application, specific attribute annotations in the source code are identified during the compiling process, the pointer ownership state conversion information and the function formal contract are generated into the structured metadata with a predefined binary format, and are written into the special metadata section of the target file (such as an ELF). In this way, the processing of the internal semantics of the program is changed from being internally digested and reformed by the compiler to being actively and standardized output to the external system, so that the technical obstacle that the program semantics information cannot be directly and reliably acquired by the external AI or verification tool is solved.

Described is a method for verifying the functional integrity of a safety controller that provides safety functions for one or more machines and has a central evaluation and control unit for operating the safety controller. The method comprises: powering on the safety controller; verifying a stored machine-readable instruction as to whether a commissioning test is to be executed; if verified, displaying information indicating that the commissioning test is to be executed; initiating a verification routine executable by the safety controller, the evaluation and control unit automatically verifying via the verification routine whether a user has successfully verified each of the safety functions; if all of the safety functions are successfully verified, deleting the machine-readable instruction that the commissioning test is to be executed; and if not all of the safety functions are successfully verified, storing the machine-readable instruction, indicating that the commissioning test is to be executed anew.

A verification device (2) includes: an expected output determination unit (24) to determine whether all output data of an inference model for an input data range constitutes a violation in that the output data are not expected outputs; an input range splitting unit (25) to split a range determined to be non-violating within the input data range and to designate a split range as the input data range that is new to the inference model; a range ratio calculation unit (27) to calculate a ratio of a range for each of the determination results with respect to the input data range; and a display processing unit (28) to display verification result information indicating the ratio of the range on a display device (6).

To provide a performance verification method, a performance verification program, and a performance verification system that link a three-dimensional model of a structure with data to be used in performance verification of a structure, and that reduce work required for performance verification and improve reliability.SOLUTION: A performance verification method includes: a three-dimensional model setting step S1 for setting a three-dimensional model of a structure having a space constituted of members, in a three-dimensional model system; a data extraction step S3 for extracting data indicating conditions related to the space or the members, from the three-dimensional model; and a calculation step S5 for calculating by inputting the data extracted in the data extraction step S3 to a conditional expression prepared in advance, by using a calculation program for verifying a performance of a structure.SELECTED DRAWING: Figure 1

An embodiment of the present application provides an interrupt verification method, apparatus, storage medium and device for C2F, including: obtaining test constraint conditions, and generating global configuration information and interrupt configuration information of the interrupt signal to be tested based on the test condition; generating a configuration file based on the two configuration information, the file containing a global configuration code, an interrupt configuration code and a program configuration code of an interrupt verification program, which are respectively used to configure the global registers of the simulation processor and the interrupt controller, the interrupt registers corresponding to the interrupt signal to be tested and the interrupt verification program; then, sending the configuration file to the simulation processor to complete the configuration; after the configuration is completed, sending the interrupt signal to be tested that meets the interrupt configuration information to the interrupt controller, and the interrupt controller sends the interrupt request to the simulation processor after processing; when it is detected that the simulation processor enters the interrupt verification program, obtaining the interrupt signal identifier and interrupt level, if the two are consistent with the interrupt configuration information, the verification is passed, thereby improving the test efficiency.

The invention discloses a chip verification method and device, and the method comprises the steps: determining at least one verification program needed by a chip design model corresponding to a verification chip and a memory module to which the verification program needs to be loaded, and the chip design model comprises the memory module; establishing a virtual protocol channel with the memory module through the protocol conversion module; loading a verification program corresponding to the memory module to the memory module based on the virtual protocol channel corresponding to the memory module; and starting simulation verification of the chip design model based on the verification program loaded in the memory module.