68 results about "Verification routine" patented technology

According to the kernel indirect control flow transfer dynamic verification method based on the eBPF, an eBPF attachment point of an indirect call instruction is positioned, a verification program is dynamically attached, a source address and a target address are captured to generate a compound key, and the legality of a control flow is verified in a pre-constructed BPF hash table; and meanwhile, three indirect addressing modes of a differential strategy adaptive register, an immediate operand and a memory are adopted. Based on an eBPF technology, an EV program can be dynamically loaded into a running kernel as required during running, and the characteristic of dynamic expansion of a modern kernel can be perfectly adapted; all the capabilities are constructed on a universal software mechanism of a Linux kernel and do not depend on any hardware extension; while powerful security defense is provided, extremely low overhead during operation is realized. Benefited from an innovative hybrid verification strategy and an efficient CFG storage scheme, control flow hijacking attacks in the real world can be effectively defended with extremely low performance loss.

The present invention provides a model for preoperative verification of a dental treatment plan, a verification tool, a method for manufacturing a verification model, a verification system, and a verification program. The model of the present invention has a model body, a hole specification portion, and a target model portion. A space is formed between the hole specification portion and the target model portion, and the space enables visual confirmation of a range in which a front end of a surgical tool can reach from the hole specification portion toward the target model portion, and enables visual confirmation of a range in which the front end of the surgical tool can reach from the hole specification portion in a tooth arrangement direction and a direction intersecting the tooth arrangement direction.

A device and a method for checking the switchability of an output of a control unit are shown. The method comprises determining that a time has come to execute a test routine, opening a switch connecting a voltage or current source to the output for an initial period of time, measuring the voltage or current output during at least part of the initial period, closing the switch at the end of the initial period, comparing the voltage or current profile measured during the initial period with one or more predetermined criteria that serve as indicators of the switchability of the output, and, if one or more of the predetermined criteria are met, terminating the test routine.a continuation of the verification routine by opening the switch for a second period of time which is longer than the first period of time, a measurement of a voltage or current output during at least part of the second period of time, and a comparison of the voltage or current waveform measured during the second period of time with one or more predetermined criteria which serve as indicators for the switchability of the output.

Computer-implemented method, including: Receiving a validation request in a vehicle data processing system (VCS) from a paired wireless device; Receiving facility identification information from the wireless facility; Validating the identity of the wireless device; and Sending vehicle identification information and payment-related information to the wireless device in response to validation of the wireless device's identity.

A verification device according to an embodiment includes a first determination unit and a second determination unit. The first determination unit determines whether a regular expression follows a syntax (for example, a syntax of a regular expression according to the Backus-Naur form) designated in advance. The second determination unit determines whether a condition (for example, real-world strong 1-unambiguity (RWS1U)) indicating that the processing time when the regular expression analyzes a character string is linear with respect to the length of the character string is satisfied.

The application discloses a bus-driven chip simulation excitation model for IP unit level verification, which is realized through the following processes: S1, replacing an IO register access sequence of a system software driver; S2, replacing a register timing sequence guarantee function of the driver; and S3, replacing a test excitation initialization process of a test machine, and directly calling a verification program entrance of the system software.

The invention relates to a computer-implemented method for operating a code generator for creating and implementing verified program code for calculating a neural network on a hardware environment (2) comprising the following steps: - Creating (S1) program code for calculating a neural network in a hardware environment based on a defined neural network; - Providing (S2) the created program code with a verification code, wherein the verification code, upon execution, checks the execution of the program code in the hardware environment (2) against at least one verification criterion; - Implementing and executing (S3) the program code provided with the verification code in the hardware environment (2); - Upon finding that the at least one verification criterion is met, creating (S5) the program code without the verification code; - Implementing (S6) the program code without the verification code in the hardware environment (2).

The invention discloses a verification method and device based on a shader compiler and a storage medium, and relates to the field of program detection.The verification method comprises the steps that a front-end compiler of a target shader is called to convert a to-be-verified program into an intermediate statement; determining a first instruction set executed by a central processing unit and a second instruction set executed by a graphics processor according to the intermediate statement; obtaining a first result set obtained by executing the first instruction set by the central processing unit; executing the second instruction set through a simulation back-end compiler to obtain a second result set; and verifying the second result set according to the first result set to obtain a verification result. Therefore, on the premise that a rear-end editor of an entity graphics processor is not used, various types of simulation rear-end compilers are used for verifying the to-be-verified program, and verification cost is reduced. Automatic verification of the second result obtained by the simulation back-end compiler can be realized, and the verification efficiency of the to-be-verified program is improved.

A verification apparatus for verifying an ID card is provided. The verification apparatus includes a processor configured to acquire, as a second captured image, an image obtained by capturing a verification image printed on an ID card to be verified, acquire, from a memory, a first captured image obtained by capturing the verification image and stored in the memory, and verify authenticity of the ID card to be verified by comparing density characteristics of each of the first captured image and the second captured image.

Embodiments of the present application provide a computer target object verification method, device, storage medium and related device. The computer target object verification method comprises: obtaining a public key signature, wherein the public key signature comprises a signature of a processor private key on a public key certificate, and the public key certificate comprises at least a computer public key; using a processor public key pre-configured in the processor to verify the public key signature; when the processor public key verifies the public key signature successfully, using the computer public key to verify a target signature, wherein the target signature is a signature of a computer private key on a target object; and when the computer public key verifies the target signature successfully, the target object is verified successfully. It can be seen that the computer target object verification method provided by the embodiments of the present application can be implemented by a computer while verifying the trusted root verification program or data in the processor.

The utility model provides a system for burning and reading verification chips in parallel. The system comprises a software module and at least one hardware module. The hardware module comprises a plug connector, a burning port and a burner; the software module comprises an upper computer, and the upper computer is connected with the burner and an LIN pin of the male end of the plug connector; the upper computer comprises a burning program and a reading verification program, the burning program is used for burning the target module through the burner, and the reading verification program is used for checking data in real time through the LIN port to judge whether the target module is successfully burnt or not. According to the utility model, the chip is read and verified while program burning is carried out on the chip in the same time period, so that the production efficiency and the verification accuracy can be obviously improved.

The invention discloses a complex program verification method based on nonlinear constraint local search solution, which belongs to the technical field of computer program verification, and comprises the following steps: generating an SMT-NRA formula of a program to be verified based on a verification target; constructing a linear equation set based on linear equality constraints in the formula, and performing replacement from non-free variables to free variables by solving the equation set to obtain a simplified formula; heuristic initialization based on a divide-and-conquer strategy is carried out on the simplified formula; an initial assignment value is obtained through standard random initialization and short-time search solution, or local search solution is carried out by dividing sub-formulas; performing iterative search on the initial assignment based on multi-path parallelism and adaptive neighborhood limitation; maintaining a multi-path list, adaptively determining candidate moving directions in each round, and allocating the candidate moving directions to each path to update the assignment; and judging the property of the to-be-verified program according to a final result of the iterative search and outputting a conclusion. According to the invention, efficient verification of the key program module containing complex nonlinear logic is realized.

This application relates to an air conditioning unit motherboard, a universal display board, and a verification method for the display board. The method applied to the display board includes: sequentially initiating verification to each stored unit application program through a verification program; obtaining communication data fed back by each unit application program; sequentially sending the communication data to the air conditioning unit motherboard; obtaining a response from the air conditioning unit motherboard; determining the communication data and unit application program corresponding to the response; and waking up the unit application program corresponding to the response. In this application, only the verification program and the unit application programs corresponding to each model need to be pre-stored in the display board. The verification program can then determine the unit application program corresponding to the air conditioning unit motherboard to be matched, thus completing the functional control of the air conditioning unit motherboard to be matched. The technical solution in this application allows the same display board to be adapted to air conditioning unit motherboards of different models, thereby improving the efficiency of the entire R&D lifecycle.

The application discloses a program verification metadata export method and device and a deterministic execution environment, and belongs to the field of compiling technology and formal verification. The method comprises the following steps: marking the pointer ownership state in the source code through attribute annotation; extracting the ownership conversion information and generating the structured metadata during compiling; and outputting the metadata to the special section of the compiling product, so that the memory safety of the program can be verified independently by directly reading the metadata by an external system. In order to make the exported metadata complete and inferable, a deterministic running environment composed of zero global state context, full-link memory management, capability token and deterministic execution suite is provided. In the application, specific attribute annotations in the source code are identified during the compiling process, the pointer ownership state conversion information and the function formal contract are generated into the structured metadata with a predefined binary format, and are written into the special metadata section of the target file (such as an ELF). In this way, the processing of the internal semantics of the program is changed from being internally digested and reformed by the compiler to being actively and standardized output to the external system, so that the technical obstacle that the program semantics information cannot be directly and reliably acquired by the external AI or verification tool is solved.

A verification device (2) includes: an expected output determination unit (24) to determine whether all output data of an inference model for an input data range constitutes a violation in that the output data are not expected outputs; an input range splitting unit (25) to split a range determined to be non-violating within the input data range and to designate a split range as the input data range that is new to the inference model; a range ratio calculation unit (27) to calculate a ratio of a range for each of the determination results with respect to the input data range; and a display processing unit (28) to display verification result information indicating the ratio of the range on a display device (6).

To provide a performance verification method, a performance verification program, and a performance verification system that link a three-dimensional model of a structure with data to be used in performance verification of a structure, and that reduce work required for performance verification and improve reliability.SOLUTION: A performance verification method includes: a three-dimensional model setting step S1 for setting a three-dimensional model of a structure having a space constituted of members, in a three-dimensional model system; a data extraction step S3 for extracting data indicating conditions related to the space or the members, from the three-dimensional model; and a calculation step S5 for calculating by inputting the data extracted in the data extraction step S3 to a conditional expression prepared in advance, by using a calculation program for verifying a performance of a structure.SELECTED DRAWING: Figure 1

A verifier device (200) in a remote attestation system including a prover device and a verifier device is provided. The verifier device includes: an evidence data reception unit (209) configured to receive evidence data, which is software, from a prover device that places and executes the software in a memory; a master storage unit (201) configured to store master software, which is a copy of the software; a difference extraction unit (211) configured to extract a difference between the evidence data received and the master software; a cause determination unit (213) configured to determine a cause of modification of the software based on the difference; and a cause information output unit (214) configured to output cause information indicating the cause determined.

To provide a detection system that makes it possible to detect partial discharges even if measurement data includes noise that differs depending on the environment, a parameter update system, a detection program, a verification server, a verification method, and a verification program.SOLUTION: The detection system includes an acquiring unit, a processing unit, a determining unit, and an updating unit. The acquiring unit acquires measurement data from a sensor attached to a power device to be monitored. The processing unit processes the measurement data on the basis of parameters associated with the power device. The determining unit determines whether a partial discharge is occurring in the monitored target on the basis of the processed measurement data. The updating unit updates the parameters on the basis of the same determination result on whether partial discharge is occurring among a plurality of pieces of reference measurement data, which is measurement data acquired in the past.SELECTED DRAWING: Figure 1

This application belongs to the field of electrical technology, specifically relating to a method, apparatus, device, and medium for handling faults in intelligent devices. The method includes: a terminal device sending fault performance information to a server, the fault performance information being determined based on the fault performance of the intelligent device; the server determining and sending a fault verification program corresponding to the fault performance information to the terminal device; the terminal device performing fault verification processing on the intelligent device based on the fault verification program, obtaining a fault verification result; the terminal device sending the fault verification result to the server; and the server, if the fault verification result indicates successful verification, sending a repair plan corresponding to the fault verification program to the terminal device. In this method, when a fault occurs in the intelligent device, the server determines the fault verification program based on the fault performance information fed back by the terminal device, and based on the verification result of the returned fault verification program, the cause of the fault and the specific repair plan can be determined.

We provide a verification system that can verify shipping information, which shows the components shipped for building construction, and help reduce errors. [Solution] The verification system uses a verification device 1 to verify the information on shipped components. The verification system acquires the information on shipped components (S202), acquires design information relating to the design of the target building (S203), determines the structure that constitutes the target building based on the acquired design information (S204), acquires technical information that shows the determined structure of the target building as components to be used and the technical relationships between components (S205), refers to the technical information based on the determined structure and derives the components to be used in construction as derived components (S209), and compares the derived components with the components shown in the information on shipped components (S211).

An information processing device (10) comprises: a reception unit (15B) that receives a designation of configuration information of a software product; a verification unit (15D) that, for each combination for which a dependency relationship between software components is described by the configuration information of the software product for which the designation has been received, compares the description of each software component corresponding to a constituent element of the combination with a reference corresponding to each software component corresponding to the constituent element of the combination among references collected from a source (30) of information about the software components, and verifies whether there are inconsistencies in the dependency relationships between the software components; and an output unit (15E) that outputs a result of the verification by the verification unit (15D).

By an attack estimation verification device, an attack estimation verification method, and a computer-readable non-transitory storage medium storing an attack estimation verification program, an attack-abnormality relation table is stored, a security log is acquired, an attack received by an electronic control system is estimated, it is determined whether grouping or an assumption feature of an abnormal electronic control unit is appropriate, and a notification indicating a verification result is provided.

To detect fraud committed in signature replacement.SOLUTION: An information processing apparatus acquires a first VC 8 that proves the validity of attribute information of a user by a first signature 8a verifiable by verification procedures of a first DID infrastructure 1, and a second VC 9 that proves the validity of the attribute information of the user by a second signature 9a verifiable by verification procedures of a second DID infrastructure 2. Next, the information processing apparatus verifies the second signature 9a contained in the second VC 9 by the verification procedures of the second DID infrastructure 2. Further, the information processing apparatus transmits a verification request for verifying the first signature 8a contained in the first VC 8 to verification devices 7a, 7b, ... capable of verifying the first signature 8a contained in the first VC 8 by the verification procedures of the first DID infrastructure 1, and then acquires, from the verification devices 7a, 7b, ..., verification results of the first signature 8a contained in the first VC 8.SELECTED DRAWING: Figure 1

The verifier device (200, 250) is configured to receive dynamic data or a measurement value calculated using the dynamic data from the prover device that places and executes a software in a memory, the software including the dynamic data whose content changes, receive basic data from the prover device, the basic data being capable of estimating the dynamic data that should originally be placed in the memory, store master dynamic data, whose data content changes, and which is included in master software that is a copy of the software, and master basic data, which is capable of estimating the master dynamic data, in association with each other, and verify the dynamic data or the measurement value using the master dynamic data associated with the master basic data corresponding to the basic data to output a verification result.

A control device, which controls a device equipped in a vehicle by executing a program, the control device comprising: a storage unit that stores the program; and a processor, the processor being configured to be capable of executing a verification operation of partially executing and verifying the program after starting execution of the program stored in the storage unit, and change an execution mode of the verification operation according to a load state of the processor.

The verifier device is configured to receive dynamic data or a measurement value calculated using the dynamic data from the prover device that places and executes a software in a memory, the software including the dynamic data whose content changes, receive basic data from the prover device, the basic data being capable of estimating the dynamic data that should originally be placed in the memory, store master dynamic data, whose data content changes, and which is included in master software that is a copy of the software, and master basic data, which is capable of estimating the master dynamic data, in association with each other, and verify the dynamic data or the measurement value using the master dynamic data associated with the master basic data corresponding to the basic data to output a verification result.

In some aspects, it is provided a method comprising, for example: carrying out, by the verifier entity, at least one auxiliary task using at least the at least one outcome indicated in the received information; determining, by the verifier entity and using at least one output of the at least one auxiliary task, a label for the at least one radio signal measurement associated with the at least one outcome, or determining, by the verifier entity and based on the at least one output of the at least one auxiliary task, the at least radio signal measurement associated with the at least one outcome is to be discarded; and transmitting the label and the at least one radio signal measurement to the first network node or the second network node to update the machine-learning model for the primary task.

To provide a verification system capable of surely specifying a password of an encrypted secret key of crypto assets by a round robin method.SOLUTION: The verification system 1 includes the server 5 connected to the network 9, and the plurality of verification terminals 7 and the request terminal 3 capable of communicating with the server 5 via the network 9. The request terminal 3 transmits a decryption request for a secret key of crypto assets encrypted by a password to the server 5, the server 5 manages character strings of all patterns for verifying the password in response to the decryption request and transmits a verification request including different unverified character strings to at least some of the plurality of verification terminals 7, and when each of the plurality of verification terminals 7 receives the verification request, the verification terminal 7 verifies the unverified character string based on the received verification request and transmits a result of the verification to the server 5.SELECTED DRAWING: Figure 1

This application relates to an interrupt verification method, apparatus, system, device, storage medium, and program product, applied to an interrupt verification device. The method includes: first, injecting an interrupt verification program into a microcontroller under test (MCU), wherein the MCU is communicatively connected to the interrupt verification device; then, receiving interrupt information sent by the MCU according to the interrupt verification program, and sending an interrupt signal to the MCU according to the interrupt information to instruct the MCU to execute the interrupt service routine corresponding to the interrupt signal; finally, outputting the interrupt verification result of the MCU based on the result of the MCU executing the interrupt service routine. This method enables interrupt verification through simultaneous hardware and software verification, rather than simply simulating interrupts in software, thus achieving higher accuracy in interrupt verification.