Semiconductor package
A semiconductor and vacuum sealing technology, which is applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as reduction, semiconductor substrate fracture, heat cycle resistance, etc.
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Embodiment approach 1
[0029] figure 1 It is a plan view showing the semiconductor package according to the first embodiment. figure 2 is along figure 1 Sectional view of the I-II section. image 3 is along figure 1 Sectional view of the III-IV cut. Devices 2 , wirings 3 , and pads 4 are formed on the main surface of a semiconductor substrate 1 made of, for example, Si. The device 2 includes, for example, sensors such as imaging elements, circuits, and the like. Pad 4 is connected to device 2 via wiring 3 . A passivation film 5 such as SiN is formed on the semiconductor substrate 1 so as to cover the device 2 , the wiring 3 , and the pad 4 . An opening is formed in the passivation film 5 on the pad 4 to expose the central portion of the upper surface of the pad 4 . The passivation film 5 on the device 2 can also be processed locally or globally. For example, when the device 2 includes an imaging element, localized processing may be performed to realize an inner lens, or a thin film may be p...
Embodiment approach 2
[0038] Figure 4 It is a sectional view showing the semiconductor package according to the second embodiment. In this embodiment, the dummy wiring 11 is formed on the same layer as the wiring 3 on the semiconductor substrate 1 , and both have the same thickness and material. In this case, since the dummy wiring 11 and the wiring 3 can be formed at the same time, it is not necessary to add an additional manufacturing process for the formation of the dummy wiring 11 . In addition, the thickness of the passivation film 5 is generally set to 0.5 μm to several μm, which is very thinner than the thickness of the sealing metal layer 7 . Therefore, even with the configuration of the present embodiment, the stress transmission suppression effect of the first embodiment can be obtained. Other configurations and effects are the same as those in Embodiment 1.
Embodiment approach 3
[0040] Figure 5 It is a plan view showing the semiconductor package according to the third embodiment. Figure 6 is along Figure 5 Sectional view of the V-VI section. The stress increases not only in the outer portion of the corner portion 10 of the sealing metal layer 7 but also in the inner portion. Therefore, in the present embodiment, the dummy wiring 11 is also formed between the inner portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1 . Since the transfer of stress from the sealing metal layer 7 to the semiconductor substrate 1 can be further suppressed by the dummy wiring 11, the heat cycle resistance can be further improved. Other configurations and effects are the same as those in Embodiment 1.
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Abstract
Description
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Application Information
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