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RRAM array summation operation circuit and method

A computing circuit and array technology, applied in the field of circuits, can solve the problems of area consumption and large width-to-length ratio of current mirrors.

Active Publication Date: 2022-04-05
SHANGHAI INTEGRATED CIRCUIT EQUIP & MATERIALS IND INNOVATION CENT CO +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Another way is to use the current mirror to amplify the currents of each channel and add the corresponding weight multiples, and then perform ADC quantization on the total current, but the current mirror with high weight has a large "width-to-length ratio", which consumes a lot of area

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  • RRAM array summation operation circuit and method
  • RRAM array summation operation circuit and method

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Embodiment Construction

[0047] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the present invention Examples, not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. As used herein, "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other el...

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Abstract

The invention provides an RRAM array summation operation circuit and method, and the circuit comprises a current input unit which is used for providing a plurality of to-be-operated currents; the first current mirror unit is electrically connected with the current input unit and is used for scaling the multiple paths of to-be-calculated current according to a first proportion and then outputting the multiple paths of to-be-calculated current; the second current mirror unit is electrically connected with the first current mirror unit and is used for scaling the current output by the first current mirror unit according to a second proportion; the third current mirror unit is electrically connected with the first current mirror unit and the second current mirror unit and used for scaling and maintaining the current output by the second current mirror unit according to a third proportion; and the output unit is electrically connected with the second current mirror unit and is used for scaling the current of the second current mirror unit according to a preset proportion and then outputting the scaled current of the second current mirror unit. According to the invention, weighted summation of multi-channel array current can be completed with relatively low power consumption, and errors can be effectively reduced.

Description

technical field [0001] The invention relates to the field of circuit technology, in particular to an RRAM array summing operation circuit method. Background technique [0002] Memristor, the full name of memristor, is a resistive random access memory (RRAM) made of memristor, which is realized between a high resistance state and a low resistance state by the resistance of a non-conductive material under the action of an applied electric field. reversible conversion based non-volatile memory. It is a circuit device that represents the relationship between magnetic flux and charge. Memristor has the dimension of resistance, but unlike resistance, the resistance value of memristor is determined by the charge flowing through it. Therefore, by measuring the resistance value of the memristor, the amount of charge flowing through it can be known, thereby having the effect of memorizing charge. Due to the nonlinear nature of memristor, chaotic circuits can be generated, so there ...

Claims

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Application Information

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IPC IPC(8): G05F3/26
CPCG05F3/26Y02D10/00
Inventor 余学儒李琛段杰斌田畔张飞翔
Owner SHANGHAI INTEGRATED CIRCUIT EQUIP & MATERIALS IND INNOVATION CENT CO