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Storage master control architecture and flash memory particle control method

A technology of flash memory particles and control modules, which is applied in the storage field, can solve problems such as inability to apply flash memory particles, and achieve the effect of improving read and write performance

Pending Publication Date: 2022-04-12
武汉喻芯半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of this application is to provide a storage master control architecture, which solves the problem that a storage master control architecture in the prior art cannot be applied to different types of and page capacity of flash memory particles and greatly improve the read and write performance of the storage master control architecture

Method used

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  • Storage master control architecture and flash memory particle control method
  • Storage master control architecture and flash memory particle control method
  • Storage master control architecture and flash memory particle control method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] figure 1 A specific structure of a storage master control architecture in this embodiment is shown. Such as figure 1 As shown, the storage main control architecture is used to adapt to flash memory particles of different types and page capacities, including a high-speed storage main control interface module, an adjustable cache and control module, a write data channel processing module, a read data channel processing module, Flash interface module and firmware control module.

[0043] Among them, the high-speed storage main control interface module is used to receive signals from the HOST host and data to be written or read, and supports multiple storage main control interfaces with different functions, including but not limited to MMC / eMMC, SD, TF, UFS , USB interface, etc. The high-speed storage main control interface module analyzes the received information to obtain information such as high-speed data link control signals, address signals, data signals, and diffe...

Embodiment 2

[0052] figure 2 The frame structure of the adjustable cache and control module in this application is shown. Such as figure 2 As shown, on the basis of Embodiment 1, each functional module in the adjustable cache and control module (Switch Buffer Control) includes a control module that parses input instructions and controls data processing, a data alignment module (DataAlign), and an adaptive Adjust the caching module. Wherein, the control module is used to analyze input instructions and control data processing; the data calibration module is connected to the control module; the adaptively adjustable cache module is connected to the control module, and the adaptively adjustable cache module can be divided into different capacities cache interval. The self-adaptively adjustable cache module processes various information signals and data information generated after proofreading according to the firmware program (Firmware), discriminates and decodes the flash storage particl...

Embodiment 3

[0054] image 3 It shows the frame structure of the write data channel processing module in this application. Such as image 3 As shown, on the basis of Embodiment 1, the data channel processing module includes a Buffer write control interface module, a data write instruction analysis module, a write instruction state machine conversion and processing module, an ECC encoding module, and a write operation and data processing module. Among them, the Buffer write control interface module is connected with the adjustable cache and control module to receive the data to be written from the cache area; the data write command analysis module is used to analyze the write command; the write command state machine conversion and processing module is used to control The state machine analyzes and judges the write instruction operation, address and data information; the data error correction encoding module is used to encode the data to be written; the write operation and data processing m...

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Abstract

The invention discloses a storage master control framework and a flash memory particle control method, and relates to the technical field of storage. The storage master control architecture is used for adapting to flash memory particles of different types and page capacities, and comprises a high-speed storage master control interface module, an adjustable cache and control module, a write data channel processing module, a read data channel processing module, a flash memory interface module and a firmware control module. By introducing a plurality of different types of adjustable cache interval designs, page size required by data processing can be adaptively configured from 1K, 2K, 4K and 8K through a firmware program, and a multi-channel processing architecture design is adopted, so that on one hand, the memory master control design can widely use a plurality of different types of flash memory particle products, and on the other hand, the memory master control design can be widely applied to a plurality of different types of flash memory particle products. According to the invention, through a parallel processing mechanism for multiple data channels of write operation (WP) and read operation (RP), the read-write performance of the storage master control architecture can be greatly improved.

Description

technical field [0001] The present application relates to the field of storage technology, in particular to a storage master control architecture and a method for controlling flash memory particles. Background technique [0002] With the rapid development of flash memory storage, multiple generations of flash memory granular products have been produced, including SLC (Single-Level Cell, single-level cell, 1bit / cell), MLC (Multi-Level Cell, multi-layer cell, 2bits / cell), TLC (Tri-Level Cell, three-layer unit, 3bits / cell) and QLC (Quad-Level Cell four-layer unit, 4bits / cell), as well as products such as 5bits / cell five-layer unit PLC that are still under development. Due to the different manufacturers and processes of each generation of products, there are also products with two-dimensional (2D) design and three-dimensional (3D) design, such as 2D SLC, 2D MLC, 3D MLC, 3D TLC, 3D QLC and other products. The data storage page size (Page Size) of each flash granule product is no...

Claims

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Application Information

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IPC IPC(8): G06F12/02G06F12/0882G06F11/10
Inventor 刘世军
Owner 武汉喻芯半导体有限公司
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