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Soft constraint enabling control method based on System verilog

A control method and soft constraint technology, applied in software reuse, faulty computer hardware detection, creation/generation of source code, etc., can solve the difficulty of test code reuse, tape-out failure of major functions, and the trouble of chip function convergence, etc. problems, to achieve the effect of improving fast computing capabilities, ensuring random distribution, and solving random value anomalies

Pending Publication Date: 2022-05-13
芯河半导体科技(无锡)有限公司
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Problems solved by technology

[0005] In chip R&D testing, unreasonable use of soft constraints leads to abnormal random values
The incorrect distribution of random values ​​will undoubtedly bring troubles to the convergence of chip functions, and may also lead to tape-out failures or major functional defects, which will cause huge economic losses to the company and bring huge technical pressure to the R&D personnel.
Although the above problems can be avoided by using hierarchical references to change member variables during the development process, this brings difficulties to the reuse of test codes

Method used

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  • Soft constraint enabling control method based on System verilog

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Embodiment Construction

[0020] Such as figure 1 As shown, the present invention discloses a soft constraint enabling control method based on System verilog, comprising the following steps:

[0021] 1) Use soft constraints when constraining random variables in the constraint body;

[0022] 2) When using constraint body soft constraints, reasonably arrange the priority of the constraint body;

[0023] 3) When soft constraints bring random exceptions, disable the low-priority constraint variables. The constraint body is a set of relational expressions used to determine the range of variable values, and the value of the relational expressions is always true.

[0024] Before using soft constraints correctly, you must first understand the differences between soft constraints and hard constraints. If many hard constraints are used in the test code, it is very likely that the solution of the System Verilog constraint solver will be abnormal. That is, if the variables of the constraint body are contradict...

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Abstract

The invention relates to the technical field of chips, in particular to a Systemverilog-based soft constraint enabling control method, which comprises the following steps of: firstly, using soft constraint when a random variable is constrained in a constraint body; when the soft constraint of the constraint body is used, the priority of the constraint body is reasonably arranged; and finally, when the soft constraint brings random exception, enabling of the constraint variable with the low priority is closed. According to the method, the problem of random value abnormity caused by unreasonable use of soft constraints in chip research and development tests is solved.

Description

technical field [0001] The invention relates to the field of chip technology, in particular to a system verilog-based soft constraint enabling control method. Background technique [0002] Compared with early verification languages ​​such as OpenVera, E language, and System C, System verilog has very important advantages, such as: object-oriented syntax, powerful assertion capabilities, powerful verification methods, and strong constraint capabilities. As far as the powerful constraint function is concerned, it can ensure precise control of randomization in the process of random testing, making System Verilog have better flexibility and stability in randomization. As an important part of soft constraints, its precise control can ensure the reusability and completeness of test codes. [0003] Although System verilog has excellent CRT (Constraint random tests) capabilities, it is easy for verifiers to ignore the random values ​​after constraints, resulting in low code coverag...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F8/36
CPCG06F11/2236G06F8/36
Inventor 张宁
Owner 芯河半导体科技(无锡)有限公司
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