In-memory computing device for multi-bit input and multi-bit weight multiply-accumulate

Abstract

The invention relates to a multi-bit input and multi-bit weight multiply-accumulate in-memory computing device, which belongs to the technical field of in-memory computing, and comprises a plurality of in-memory computing sub-devices, and each in-memory computing sub-device comprises an input conversion module, a weight array, a digital time converter and a computing unit; the input conversion module is used for converting a multi-bit digital input value into an analog voltage; the weight array is connected with the digital time converter; the weight array is used for providing a multi-bit weight, the digital-to-time converter is used for generating a weighted pulse signal according to the multi-bit weight and an input pulse signal, the computing unit is used for multiplying and accumulating the analog voltage and the weighted pulse signal, converting a multi-bit digital input value into the analog voltage, and outputting the analog voltage and the weighted pulse signal. The weighted pulse signal is generated according to the multi-bit weight and the input pulse signal, the analog voltage and the weighted pulse signal are multiplied and accumulated, and the calculation speed is increased.

Description

technical field [0001] The invention relates to the field of in-memory computing, in particular to a multi-bit input and multi-bit weight multiply-accumulate in-memory computing device. Background technique [0002] In recent years, artificial intelligence (AI) has increasingly demanded energy-efficient computing systems, including edge intelligence and its applications, and DNNs in AI systems require a large number of parallel product (MAC) operations. During MAC operation, a large amount of weights and intermediate output data transfer is unavoidable between the processing unit (PE) and the memory, which leads to unavoidable power consumption and delay, which limits certain AI applications such as battery powered edge devices. Hence, compute-in-memory (CIM) architectures have emerged to perform energy-efficient parallel MAC operations by concurrently accessing multiple cells on a bit line (BL) of in-mold memory. This greatly reduces the amount of intermediate data genera...

AI Technical Summary

Problems solved by technology

The calculation method of single-bit input multiplied by single-bit weight is inefficient, and a single calculation unit consumes a large number of transistors, and the multiplication and accumulation of too many single-bit calculation units in the same column will make it difficult to accurately quantify the analog calculation voltage; The implementation method usually adopts multi-cycle cyclic limited bit accumulation, which leads to a long time to complete multi-bit calculation, and does not improve the calculation energy efficiency to a certain extent.

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