Integrated circuit with embedded memory module

Abstract

The present disclosure relates to a system and method for maintaining stability during scan shift operations on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit (100) including a plurality of memory modules (1011-n) and a built-in self-test (BIST) controller (102), where the BIST controller and memory modules are arranged and configured to reduce switching of cells in the memory modules during scan shift operations.

Description

technical field [0001] The present disclosure relates to a system and method for maintaining stability during scan shift operations on multiple embedded memories in an integrated circuit. Background technique [0002] An integrated circuit (IC) may include embedded memory. In some cases, particularly where larger memory capacities are required, the memory may be divided into multiple smaller memory modules distributed throughout the IC. This can reduce power consumption. However, using multiple memory modules does require the use of more boundary logic, such as a test multiplexer, for each memory address. In a scan shift operation, the normal operating mode of the IC is suspended, and multiple flip-flops in the IC are connected as long shift registers. This enables serial input test patterns to be loaded into scan chains formed from flip-flops using a single input pin. Move the result out of the scan chain and compare it to the expected result to verify that the IC is wo...

AI Technical Summary

Problems solved by technology

However, such solutions may require additional hardware or may degrade the performance of the IC and may affect the functionality of the scan test timing path

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