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Localized parallel computing architecture and method based on MPICH + OPENMP

A parallel computing and algorithm technology, applied in the direction of user interface execution, multi-programming device, resource allocation, etc., can solve the problems of poor stability and flexibility of MPI, OpenMP only supports a single computing node, etc., to achieve good stability and flexibility Effect

Pending Publication Date: 2022-07-15
BEIJING INST OF COMP TECH & APPL
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  • Application Information

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Problems solved by technology

[0006] The technical problem to be solved by the present invention is how to provide a localized parallel computing architecture and method based on MPICH+OPENMP to solve the problem of poor parallel stability and flexibility of traditional MPI, while OpenMP only supports a single computing node

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  • Localized parallel computing architecture and method based on MPICH + OPENMP
  • Localized parallel computing architecture and method based on MPICH + OPENMP
  • Localized parallel computing architecture and method based on MPICH + OPENMP

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Embodiment Construction

[0059] In order to make the purpose, content and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0060] The invention relates to a localized parallel computing architecture and method based on MPICH+OPENMP. The invention is constructed based on the MPICH+OpenMP hybrid architecture, and achieves the effect of improving computing efficiency by realizing hybrid parallel acceleration for computing algorithms. Coarse-grained parallelism based on MPICH parallel architecture realizes parallel computing between nodes, including tasks distribution among nodes, data collection synchronization and other functions. The fine-grained parallel computing based on the OpenMP parallel architecture realizes the parallel computing at the algorithm level between the CPU cores inside the node. The parallel acceleration platform can be flexibly appli...

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Abstract

The invention relates to a localized parallel computing architecture and method based on MPICH + OPENMP, and belongs to the field of parallel computing. The method is based on MPICH + OpenMP hybrid architecture construction, and the effect of improving the calculation efficiency is achieved by achieving hybrid parallel acceleration of a calculation algorithm. Coarse grain parallel based on the MPICH parallel architecture realizes parallel computing among nodes, and has the functions of task distribution among the nodes, data collection and synchronization and the like. And parallel computing of an algorithm level between CPU cores in the nodes is realized based on fine grain parallel computing of the OpenMP parallel architecture. The parallel acceleration platform can be flexibly applied to domestic hardware platforms such as Feiteng and Loongson and domestic operating systems such as Neokylin and Kylin. According to the method, the number of the parallel threads can be automatically adjusted according to the parallel computing node system resources, the parallel threads are distributed, the maximum utilization of computing power is achieved, compared with traditional MPI parallel, better stability and flexibility are achieved, and meanwhile the defect that OpenMP only supports a single computing node is overcome.

Description

technical field [0001] The invention belongs to the field of parallel computing, in particular to a localized parallel computing architecture and method based on MPICH+OPENMP. Background technique [0002] From 1986 to 2002, the performance of microprocessors increased rapidly at an average rate of 50% per year. Since 2002, the performance improvement rate has dropped to 20%. In recent years, the upper limit of clock frequency has made the speed increase of a single processor very limited as the heat dissipation capacity of cooling integrated circuits with air has reached its limit. The development of multi-core processors has become the choice of most mainstream CPU manufacturers. [0003] Traditional serial computing programs cannot fully utilize multiple processor cores. Therefore, special computing programs need to be written so that the computing power of each processor core can be fully utilized. [0004] Since the Prism Gate, the state has increased its support fo...

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Application Information

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IPC IPC(8): G06F9/50G06F9/451H04L69/164
CPCG06F9/5066G06F9/451H04L69/164Y02D10/00
Inventor 赵漫菲储一光王浩枫
Owner BEIJING INST OF COMP TECH & APPL