Error correction anti-radiation circuit design method
An error correction circuit and circuit design technology, applied in the direction of logic circuits with logic functions, can solve the problems of reducing circuit performance and large area overhead, and achieve the effect of small additional area overhead and short additional delay
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Embodiment 1
[0027] Embodiment 1 The error correction and radiation resistance circuit design based on NAND gate and OR gate, according to the following steps, wherein,
[0028] Step 1: Follow figure 1 The circuit structure shown, using the traditional integrated circuit design method to design the error correction circuit;
[0029] according to figure 1 The circuit structure shown, the error correction circuit is designed, figure 1 It contains three NAND gates A1, A3, A4 and one OR gate A2. The input ports of the NAND gate are I1 and I2, the output port is O, and the logic NAND circuit function is realized. The input ports of the OR gate are I1 and I2. The output port is O, which implements a logic or circuit function. figure 1 The NAND gates A1, A3, A4 and the OR gate A2 can all be implemented by traditional integrated circuit design methods. figure 1 , when n1 and n2 have the same value, n7 will output the value of n1. For example, when both n1 and n2 are 0, the value of n5 and n6 ...
Embodiment 2
[0033] Example 2 Test Experiment
[0034] In the experiment, the traditional standard circuit design method is used to realize six benchmark test circuits bigkey, dsip, S38417, S13207.1, S15850.1, S38584.1 [5] without radiation resistance, and then the three-mode redundancy scheme is used. [2] and the present invention implement these benchmark test circuits respectively, so that they have the ability to resist radiation. These benchmark test circuits implemented by different schemes are randomly radiated 1000 times, and the average number of errors, area and power consumption obtained by the test are shown in Table 1. The area and power consumption in Table 1 are normalized, and their values are multiples relative to the area and power consumption of the circuit implemented by the solution of the present invention. The results shown in Table 1 show that the error occurrence times of the present invention and the three-mode redundancy scheme are both less and equal, so thei...
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