A preparation method of radiation-resistant latch based on NOR gate and AND gate

Abstract

The invention belongs to the field of integrated circuits and relate to a / an NOR gate or And gate-based circuit design method for an anti-radiation latch, in particular to a / an NOR gate or And gate-based preparation method for an anti-radiation latch. According to the latch, 8 basic units formed by NOR gates or AND gates are connected in a mutually twisted manner. When a storage node value is changed due to radiation, other mutually-twisted nodes restrain this change through the NOR gates. After the radiation effect disappears, the false storage node will be driven to recover to the original correct value, so the latch has the anti-radiation fault tolerant characteristic.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a circuit design method of a radiation-resistant latch based on a NOR gate and an AND gate, in particular to a preparation method of a radiation-resistant latch based on a NOR gate and an AND gate. Background technique [0002] Studies have reported that with the reduction of the process size, the integrated circuits in the chip are more and more susceptible to errors caused by heavy particle or proton radiation in high-level space or near-Earth space; if the radiation occurs at the storage node of the latch circuit, it may Directly cause the latch to store wrong values, resulting in a single event reversal event; if the radiation occurs at the combinational circuit node, it may cause a single event transient pulse, changing the logic state of the circuit node; the error value caused by the single event transient pulse is transmitted to The latch will and may be captured to store...

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Problems solved by technology

[0003] At present, the design method of radiation-resistant latch circuit mainly includes multi-mode redundancy, error correction code and radiation-resistant hardening technology, etc. Among them, the multi-mode redundancy method is represented by triple-mode redundancy technology, using redundant circuit modules and The majority voting circuit shields the output of the wrong circuit module, but this method will bring a large area overhead; the error correction code method is represented by the Hamming code, and the location of the wrong bit is located by calculating the check value of the code; radiation resistance reinforcement The technology is represented by the double interlocking memory unit, which adds additional transistors and intertwined interconnection wires on the basis of the basic memory unit structure to enhance the radiation resistance of sensitive nodes; however, error correction codes and radiation-resistant hardening technologies will bring Larger area overhead and reduced circuit performance

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