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Grid-control Darlington electrostatic protection device and manufacturing method thereof

An electrostatic protection device and gate control technology, which is applied in the direction of electric solid-state devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of different magnifications of transistors, unstable resistance values, and inapplicability, and achieve extended current The effect of circulation path, convenient operation and simple process

Pending Publication Date: 2022-07-29
HUNAN NORMAL UNIVERSITY
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Now foreign Darlington transistors have a very large resistance between the primary BE and 10Kohm, while the resistance value of Darlington transistors in domestic countertop technology is generally unstable, resulting in different transistor amplification factors. For products with high magnification requirements, domestically produced Darlington tubes are not suitable

Method used

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  • Grid-control Darlington electrostatic protection device and manufacturing method thereof
  • Grid-control Darlington electrostatic protection device and manufacturing method thereof
  • Grid-control Darlington electrostatic protection device and manufacturing method thereof

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Embodiment Construction

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] like figure 1 , figure 2As shown, a gate-controlled Darlington electrostatic protection device includes a P-type substrate 101; the P-type substrate 101 is provided with a first DN-Well region 104 on the left side, and the bottom of the first DN-Well region 104 is connected to A first NBL region 102 is arranged between the P-type substrates 101 ; a second DN-Well region 105 is arranged symmetrically with the first DN-Well region 104 on the right side of the P-type substrate 101 , and the bottom of the second DN-Well region 105 A second NBL region 103 is arranged between it and the P-type substrate 101; a first N+ implantation region 108 and a second N+ implantation region 109 are arranged on the upper surface of the first DN-Well region 104 in sequence from left to right. The DN-Well area 104 is provided with a P-Well area 106, and the P-Well ar...

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Abstract

The invention discloses a grid-control Darlington electrostatic protection device which comprises a P-type substrate, a first DN-Well region and a second DN-Well region are arranged in the P-type substrate, a first N + injection region and a second N + injection region are arranged on the first DN-Well region, a P-Well region is arranged in the first DN-Well region, a P-BODY region is arranged on the second DN-Well region, and a P + injection region, a third N + injection region and a fourth N + injection region are arranged on the P-BODY region. A first polysilicon gate is arranged between the P + injection region and the third N + injection region, and a second polysilicon gate is arranged between the third N + injection region and the fourth N + injection region. The first NPN triode and the second NPN triode form an NPN type Darlington tube structure, and after the device is conducted, the current gain is far larger than that of a single NPN tube.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a gate-controlled Darlington electrostatic protection device and a manufacturing method thereof. Background technique [0002] With the development of integrated circuit manufacturing process, engineers are more willing to select devices with the highest electrostatic discharge efficiency per unit area to improve the efficiency of integrated circuits. At present, ESD protection of integrated circuits is receiving extensive attention from those engaged in the related fields of integrated circuits. ESD surge protection is a very important challenge for high voltage applications. In a high-voltage environment, the chip must have good high-voltage and high-current tolerance. It requires a very small chip area and high ESD robustness. This is a major problem that high-voltage ESD protection designers need to solve. . Therefore, designing a highly robust on-chip integrated ESD pro...

Claims

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Application Information

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IPC IPC(8): H01L27/02H01L21/82
CPCH01L27/0248H01L27/0281H01L27/0296H01L21/82
Inventor 金湘亮包兴涛汪洋
Owner HUNAN NORMAL UNIVERSITY
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