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Circuit for generating reference voltage for reading out from ferroelectric memory

A ferroelectric memory and reference voltage technology, which is applied in the field of circuit devices for reading signals, can solve problems such as reducing signal-to-noise ratio, long time delay, and large area requirements

Inactive Publication Date: 2004-07-14
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this measure is on the one hand the relatively large area requirement and on the other hand the reduced signal-to-noise ratio due to the so-called "imprint" effect
[0009] Although this measure can generate reference signals more accurately, it requires a relatively long time delay because the generation of each signal is a series of processes.

Method used

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  • Circuit for generating reference voltage for reading out from ferroelectric memory
  • Circuit for generating reference voltage for reading out from ferroelectric memory
  • Circuit for generating reference voltage for reading out from ferroelectric memory

Examples

Experimental program
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Embodiment Construction

[0029] Figure 7 to 9 It has been explained in the previous article. In the figure, the same symbols are used for the corresponding components and signal processes.

[0030] in figure 1 In the circuit arrangement, the bit lines B1 and B2 at time t0 (see figure 2 ) Through the pre-charge wires VE and VL ("pre-charge") are both maintained at half the power supply potential VCC / 2. To this end, the bit lines B1 and B2 are connected to the wires VL and VE through the transistors T7, T8, and T9.

[0031] At time t1, the bit lines B1 and B2 are precharged to 0V by changing the wire VE to 0V.

[0032] At time t2, by putting the word line W i And DW1 and DW2 are connected to the bit line B2, so that the cell content of the memory cell C1 applied with the plate voltage VP is output through the transistor T5, and the content of the reference cells DC0 and DC1 with the plate voltage DVP are output through the transistor T3 and T4 is applied to the reference bit line B1. As a result, the refe...

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Abstract

The invention relates to a circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with constant plate voltage (VP) from storage cells (C1, C2) of a ferroelectric memory via bit lines (B1, B2; BLt, bBLt). In the inventive circuit, a reference voltage device is comprised of two reference cells (DC1, DC0) which are subjected to the action of complementary signals. Said reference cells can be simultaneously read out from in order to generate the reference voltage in a selection and evaluation device.

Description

Technical field [0001] The present invention relates to a circuit device for generating a reference voltage to read out and analyze a readout signal read from a memory cell of a ferroelectric memory using a constant plate voltage via a bit line. The circuit device has a reference voltage device And a selection and analysis device connected to the bit line. Background technique [0002] In dynamic write / read memory (DRAM), the read signal is well known to be located above or below the zero-valued reference potential. This is Figure 8 There is a clear description in which shows the time course of the read signal "1" and the read signal "0". In this embodiment, when the voltage value V is greater than VREF, it is "1", and when it is less than VREF, it is "0". Here, the generation of the reference signal VREF of 0V or close to 0V is relatively simple. [0003] In ferroelectric memory (FeRAM), this situation is more complicated: at this time, the two readout signals "1" and "0" are g...

Claims

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Application Information

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IPC IPC(8): G11C11/22G11C29/12
CPCG11C11/22
Inventor G·布劳恩H·赫尼格施米德T·雷尔O·科瓦里克K·霍夫曼
Owner INFINEON TECH AG