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Content addressable memory addressable by redundant form input data

A memory and data technology, applied in the field of content addressable memory

Inactive Publication Date: 2004-08-04
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] There are no known storage systems that retrieve data based on input data in redundant form

Method used

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  • Content addressable memory addressable by redundant form input data
  • Content addressable memory addressable by redundant form input data
  • Content addressable memory addressable by redundant form input data

Examples

Experimental program
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Embodiment Construction

[0026] The present invention provides a content addressable memory that compares the value of input data in redundant form with non-redundant form of data stored therein. CAM decodes redundant form data within the data decoder. Thereafter, CAM compares and detects the decoded data. The speed of decoding and comparison detection of the invention is faster than traditional adders, even faster than complete redundant form adders.

[0027] Figure 5 A CAM 200 constructed in accordance with an embodiment of the present invention is illustrated. CAM 200 includes a data decoder 210 and a plurality of registers 220 . Data decoder 210 receives input data in redundant form [= m - m+n ] and decode to a data signal. The decoded redundant form data is input to the comparison detection logic corresponding to each register ( Figure 5 not shown). CAM 200 generates an output indicating which register, if any, stores the same data value as the input data in redundant form.

[0028...

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Abstract

A content addressable memory(200)compares the value of redundant form input data to non-redundant form values stored in registers(220s)of the memory. The memory decodes the redundant form input data in a data decoder(210). Thereafter, the CAM performs match detection on the decoded data. The decoding and match detection are performed more quickly than traditional adders and even more quickly than complete redundant form adders.

Description

technical field [0001] The present invention relates to a content addressable memory adapted to use redundant forms of input signals. Background technique [0002] It is a goal of a storage system to fulfill requests for stored data with as little delay as possible. Often, the requesting agent cannot proceed further without the requested information. This criterion also applies to content-addressable memories ("CAMs"). [0003] Increasingly, however, algorithmic operations are part of storage operations. That is, a data request defines one or more arithmetic operations, the results of which are applied to memory as addresses. All the time to complete the algorithm is counted towards the latency of the storage request including the operation of the algorithm. Thus, reducing the time required to perform all of the algorithmic operations involved in a storage request becomes a goal of the storage system. [0004] Figure 1 illustrates a conventional adder circuit. Here, tw...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/38G11C15/00G11C15/04
CPCG11C15/00G11C15/04G06F7/38
Inventor D·J·萨格尔
Owner INTEL CORP