Multiphace clock generating circuit

Abstract

A multi-phase clock generation circuit includes a clock generation circuit, first frequency divider circuit, first clock selection circuit, second to nth frequency divider circuits, second to nth clock selection circuits, and clock selection control section. The clock generation circuit generates 2n (n is a positive integer) reference clock signals having the same frequency and different phases. The frequency divider circuit frequency-divides one of the reference clock signals by 2 to generate clock signals 180 DEG out of phase with each other. The first clock selection circuit selects one of each of the clock signals and a corresponding reference clock signal and outputs the selected signals as clock pulses. Each of the second to nth frequency divider circuits frequency-divides a clock pulse to generate clock signals 180 DEG out of phase with each other. Each of the second to nth clock selection circuits selects one of each of the clock signals and a corresponding one of the reference clock signals to output the selected signals as clock pulses. The clock selection control section controls the first to nth clock selection circuits in accordance with a set frequency division ratio.

Description

technical field [0001] The present invention relates to a multi-phase clock generation circuit for generating multi-phase clock pulses, in particular to a multi-phase clock generation circuit for generating multi-phase clock signals by frequency division of clock signals. Background technique [0002] Recently, with the development of the Internet and various communication networks, the amount of communication traffic has increased dramatically. In order to accommodate an extremely large amount of information, communication equipment such as routers and servers handling such information is required to be capable of high-speed interconnection between semiconductor elements, semiconductor devices (chips), or units constituting the communication equipment. To realize such high-speed interconnection, high-speed serial transmission technology is used, which increases the transmission speed of each channel in communication LSI (Large Scale Integration) to the order of several giga...

AI Technical Summary

Problems solved by technology

[0031] As mentioned above, in order to Figure 15 In the shown multi-phase clock generating circuit 161, to select one of the multi-phase clocks with different frequency division numbers, for example, Figure 16 circuit configuration shown in, resulting in an increase in the circuit scale size

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