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Bit line controlling decoder circuit, semiconductor storage device and data reading method thereof

A semiconductor and decoder technology, applied in the field of data readout, which can solve problems such as misreading and leakage current prevention

Inactive Publication Date: 2006-01-04
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

this may cause misinterpretation
Moreover, there is a problem that high-speed readout is prevented by leakage current flowing to adjacent cells even before misread occurs.

Method used

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  • Bit line controlling decoder circuit, semiconductor storage device and data reading method thereof
  • Bit line controlling decoder circuit, semiconductor storage device and data reading method thereof
  • Bit line controlling decoder circuit, semiconductor storage device and data reading method thereof

Examples

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Embodiment Construction

[0101] The present invention will be described in detail below based on the embodiments shown in the accompanying drawings.

[0102] figure 1 A structure of a memory array of a virtual ground type nonvolatile semiconductor storage device of one embodiment is shown. The memory array is virtually grounded, with one of the blocks of the memory array shown on the diagram. ACT (Asymmetric Contactless Transistor) cells are called memory cells.

[0103]The ACT unit works as follows. It should be noted that FT (Fowler-Nordheim) tunneling is used for writing and erasing. First, read and verify operations will be described. Read and verify operations are performed in the same manner. During readout, such as Figure 9A As shown, a read voltage (verification voltage) is applied to the write line WL of the transistors constituting each memory cell, and a voltage of 1 volt is applied to the source side sub-bit line SB. Then, the sense amplifier performs sense amplification to determ...

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PUM

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Abstract

There is provided a virtual ground type nonvolatile semiconductor storage device capable of effectively suppressing a leak current to the adjacent cell and thereby achieving high-speed read. During read operation, a ground potential GND is applied to a bit line SBL5 connected to the source region of one memory cell transistor MC04 subjected to read. Moreover, a read drain bias potential Vread is applied to a bit line SBL4 connected to the drain region of the memory cell transistor MC04. A bit line SBL3 connected to the drain region of a first adjacent memory cell transistor MC03 is put into a floating state. A potential Vdb equal to the read drain bias potential Vread is applied to a bit line SBL2 connected to the drain region of a second adjacent memory cell transistor MC02.

Description

technical field [0001] The present invention relates to a bit line control decoder circuit, a virtual ground type nonvolatile semiconductor storage device equipped with the decoder circuit, and a data readout method of the virtual ground type nonvolatile semiconductor storage device. Background technique [0002] In recent years, with the development of functions of portable telephones and the expansion of the memory card and file markets, flash memory capacity is increasing, and devices with small effective cell areas are being continuously developed, (such as multi-valued systems and virtual ground array systems ) in order to solve the problem of cost reduction. Specifically, the virtual ground array system can achieve a small unit area by designing its circuits, thereby allowing the development of devices with a small chip area through the same process. However, due to the virtual ground structure, it cannot be ignored that the memory cell to be rea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/00G11C16/06G11C11/40G11C16/04G11C16/08G11C16/26
CPCG11C16/26G11C16/0491G11C16/08G11C11/40
Inventor 山本薰伊藤伸彦
Owner SHARP KK
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